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STD PLL_Lesson_190805
PLL_Lesson_190805
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Update time：
2016-08-14 06:28:35
Creation time：
2016-08-05 11:16:02
Description
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Design Drawing
Design Drawing
schematic diagram
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New Schematic
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2xHALF74HC112EE
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74HC73EE symbol with model test jig
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74HC112EE symbol with model test jig
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74HC4040EE symbol with model test jig
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SCHMITTNAND2EE gated oscillator test jig with symbol
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AND3EE test jig with symbol
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DFFEE D type flip flop demo
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DFFEE D type flip flop demo
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Wallman amplifier circuit
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PhaseDetecion
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PCB
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| ID | Designator | Quantity |
|---|---|---|
| 1 | U1 | 1 |
| 2 | V1 | 1 |
| 3 | V2 | 1 |
| 4 | V1 | 1 |
| 5 | V2 | 1 |
| 6 | R1,R2,R3,R4 | 4 |
| 7 | C1 | 1 |
| 8 | U3 | 1 |
| 9 | U2 | 1 |
| 10 | V1 | 1 |
| 11 | VCLK | 1 |
| 12 | VMR | 1 |
| 13 | R1,R2 | 2 |
| 14 | C1,C2 | 2 |
| 15 | U2 | 1 |
| 16 | VDD | 1 |
| 17 | COSC | 1 |
| 18 | ROSC | 1 |
| 19 | V1 | 1 |
| 20 | U2 | 1 |
| 21 | V2 | 1 |
| 22 | VDD | 1 |
| 23 | RSOURCE2,RLOAD,RSOURCE1,RSOURCE3 | 4 |
| 24 | V1 | 1 |
| 25 | V3 | 1 |
| 26 | U1 | 1 |
| 27 | VNETLINK | 1 |
| 28 | V1 | 1 |
| 29 | VCLK1 | 1 |
| 30 | VSET1 | 1 |
| 31 | VRESET1 | 1 |
| 32 | U1,U2 | 2 |
| 33 | Q1,Q2 | 2 |
| 34 | R1,R4 | 2 |
| 35 | R2 | 1 |
| 36 | R3 | 1 |
| 37 | RC | 1 |
| 38 | RE | 1 |
| 39 | R5,RLOAD | 2 |
| 40 | C1,C4,C2 | 3 |
| 41 | C8,C6 | 2 |
| 42 | C3,C7,C5 | 3 |
| 43 | V1 | 1 |
| 44 | V2 | 1 |
| 45 | V2 | 1 |
| 46 | VCLK2 | 1 |
| 47 | U3 | 1 |
| 48 | U4,U5 | 2 |
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