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STD J-Link V9 mini (Mod)
J-Link V9 mini (Mod)
License
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Update time：
2024-12-25 08:07:36
Creation time：
2024-12-22 07:52:02
Description
Description
Debugger jlink v 9 mini https://github.com/SWUST-ESLAB/JLink-V9-mini (modification).
Additional information can be found at the following links:
https://github.com/xxl1998/JlinkV9
https://github.com/Misaka0x2730/RailLink
Slots with aspect ratio of 2.00 were detected in your design. This could increase the risk of incomplete drilling of the slot, which
decrease manufacturing efficiency and yield, and affect the reliability of the boards. The ratio should be increased to at least 2:1
Design Drawing
Design Drawing
schematic diagram
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PCB
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | 10u | C1,C2 | CASE-B_3528-A | 2 |
| 2 | 0.1u | C3 | C0805 | 1 |
| 3 | 2.2u | C4,C5 | C0805 | 2 |
| 4 | 1N5819W | D1 | SOD-123FL_L3.4-W2.4-LS3.9-RD | 1 |
| 5 | SRV05-4-N | D2 | SOT-23-6_L2.9-W1.6-P0.95-LS2.8-BR | 1 |
| 6 | HDR-M-2.54_1x4 | J1,J2 | HDR-M-2.54_1X4 | 2 |
| 7 | HDR-M-2.54_1x5 | J3 | HDR-M-2.54_1X5 | 1 |
| 8 | LED 1608 | LED1,LED2,PWR | LED1608 0526 2022 | 3 |
| 9 | (IDC-10MS) | P1 | IDC-10MS (BH-10) | 1 |
| 10 | MMBT3904LT1G | Q1 | SOT-23-3_L2.9-W1.6-P1.90-LS2.8-BR | 1 |
| 11 | 1,5k | R1,R28 | R0603 | 2 |
| 12 | 10k | R2,R3,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,R16 | R0603 | 13 |
| 13 | 220 | R4,R5,R31 | R0603 | 3 |
| 14 | 100 | R17,R18,R19,R20,R21,R22,R23,R24,R25,R26,R27,R29,R30 | R0603 | 13 |
| 15 | STM32F205RET6TR | U1 | LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL | 1 |
| 16 | AMS117-3.3V (RAM) | U2 | AMS117-TOPL | 1 |
| 17 | 918-418K2023S40019 | USB1 | TYPE-C-SMD_918-418K2023S40019 | 1 |
| 18 | 12MHz | X1 | OSC-SMD_3P-L3.2-W1.3-P1.2-L | 1 |
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