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Std edition Simple Z80 SBC

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License: GPL 3.0

Published Time: 2021-12-16 02:12:20
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Simple Z80 test design - single board with all the basics and a few luxuries.

NOTE EasyEDA shows the most recent WIP for this project, which might be part way through me making changes. Before using the PCB layout please do get in touch (comment or message) so I can let you know if what you're seeing is stable! I create labelled versions of the project, but EasyEDA doesn't allow me to publish a specific version :-(

Please do post comments down below if you find any of this interesting, I'd love to share thoughts on how this could be improved in future! I've noticed a few people have cloned it and a few have starred so I'd love to hear from you all.

The board has many more options than it really needs so that I can experiment. All devices are through-hole to make the build easy for those of us yet to venture into SMD. Influences for this project include the RC2014 512K RAM/Flash card and the SIO/2 card along with bits and pieces from all over the Internet that I've managed to lose track of.

The paged memory model supports a 4MB address space, 1MB of which is used on board. The main header exports all Z80 control lines plus the extended address bus allowing 3MB external. I'm hoping to add a memory mapped video card along the lines of the 70s/early 80s systems which would sit in the paged memory map. Great for simple games!

The board uses an oscillator chip and an optional divide by 2 to the CPU and SIO. This allows a certain level of exprimentation with clock speeds. I'm using a 10MHz Z80/SIO/CTC and on the first version of the board a 7.35MHz clock. With the CTC it's possible to decouple the system clock from the SIO baud rate so it's easier to play with clock speeds. I'm hoping to use at least a 10MHz clock or possibly higher. I have a 25MHz clock which, with the divide by 2 might work quite nicely. It's also possible to drive the clock externally rather than use the on board one. So I could have a video card with 25MHz dot-clock also driving the main board. Lots of options!

update the board is working nicely and I have it running at 14.7456MHz crystal.

Version 2 board features:

  • 512K SRAM + 512K Flash memory in 16K pages and 4M address range
  • SIO/0 dual UART
  • Z80 CTC
  • SD Card interface. Pins suitable for the breakout board I have.
  • (2.2) second SD Card interface. Allows two cards but more importantly easy copying between them for cloning. The second connector could also be used for any SPI peripheral with suitable software.
  • Exported SPI interface. Includes two spare device select lines, also exported, allowing connection to external SPI devices
  • DS1704+ real time clock with battery backup
  • i2c interface (used for the clock and available on headers to connect external devices)


The banked memory system means there's plenty of space. I have CP/M 2.2 running from SD Card and a boot loader that supports a range of functions including booting from a Raspberry Pi over the second serial port, or booting directly from SD Card. It's a bit of a mess at the moment but once it's cleaned up it'll be on GitHub.


  • The BOM needs some tidying up including renaming components for consistency. It's a pain doing this on EasyEDA because renaming causes the PCB to think it's a new component and loses all the existing layout.
  • Move some of the circuits around to make each schematic page do one logical thing
  • Add a "RESET IN" signal on the connector to allow an external system (eg Raspberry Pi) to force a hardware reset. This with a Bluetooth serial adapter would allow completely remote devevlopment.

Change Log version 2.2

Bug fixes from the version 2.1 board:

  • The CPU "WAIT" should be pulled high. It wasn't on version 1 and caused no problem (luck I think!) but should be. There are spare resistors in RP1 so a link to one of those fixes this potential issue.
  • BRDM should be (/MREQ OR BA21),it's incorrectly (/WR OR BA21). Also the second input to BR21SEL should be /MREQ not /WR. Patch for version 2.1: remove BR21SEL jumper and connect the centre pin the MREQ. This limits the addressable memory range to 2M (1 external) rather than 4 but is OK.
  • Silkscreen error: mux_2 should be a 74HCT138, NOT 139!!


  • Shrink board size a bit. This reduces build costs for the board. Current WIP 2.2 is 20% smaller in area than 2.1
  • Add connector for a second SD Card to allow card-to-card copies
  • Extend output port 64h to 8 bits. Upper 8 bits select a further 4 SPI devices. Allows efficient access to the second SD card and other SPI devices and minimises changes to SD card library.
  • Change oscilator layout to accept both 8 bit and 14pin layouts. All my 7MHz parts are 14 pin and my 14MHz parts are 8 :/
  • The CR2032 battery holder I used seems to have availability issues. Change layout to accept several different layouts.
  • Not everyone is going to want a CTC so should be able to leave that out. If you do that then really you want to bridge IO_1 to IOUT to allow the interrupt chain to be maintained on external cards. Add a jumper between these two. (New jumper P5)
  • Allow SIO - port B to be driven from the CTC or CLKU. 2.1 it was only driven by CLK, the CPU frequency.
  • Allow SIO - port A to be driven either from the CTC or from CLKU. 2.1 allowed only CLKU and not the CTC for port A.
  • Include option (link) to divide SIO port A Tx to 3V rather than 5. This would allow direct connect to 3.3V devices. There are some serial to Bluetooth adaptors this would be useful for.
  • Add support for BOTH SIO/0 (current design) and SIO/2 which seems more popular if less available. Only three pins change function.
  • Add a "RESET IN" signal on the connector to allow an external system (eg Raspberry Pi) to force a hardware reset. This with a Bluetooth serial adapter would allow completely remote devevlopment.

Changelog 2.1

Bug fixes:

  • Fix layout for 74HCT04 - Incorrect 16 pin package used. Replaced with correct 14 pin package.
  • Pull up control lines (INT and others) - missing ulls ups result in unpredicatably behaviour.

Changes from version 1 to version 2

  • Add SPI interface
  • Add i2c interface
  • Add i2c real time battery backed clock (DS1307+ chip)
  • Add SDCard hardware interface (single card)
  • Add optional clock divider - selected by jumper. Select either full oscillator speed or 1/2.
  • Add Z80 CTC
  • Remove LED bar. Required too much logic to drive.


With the SDcard interface working very nicely maybe the board doesn't need 512K of flash. It's a complete PITA to programme compared with simply writing to the SD card. Maybe a smaller flash device?

design drawing
schematic diagram
1 /
1 /
ID Name Designator Footprint Quantity
1 4K7 R13,R14,R4,R17,R19,R6,R5,R9,R11 AXIAL-0.4 9
2 Header-Male-2.54_1x3 SIOCLK,CPUCLK,BA21SEL HDR-TH_3P-P2.54-V 3
3 Header-Male-2.54_1x3 P3,P2 HDR-3X1/2.54 2
4 Z80CPU-P CPU DIP-40 1
5 Resistor SIL x8 RP2,RP3,RP1 SIL-9 3
6 ECS-100AX-010 OSC DIP14-QUARTZ 1
7 Z80 SIO/0 SIO/0 DIP-40-600-ELL 1
8 Male Header 2.54mm PWR 2.54MM_HDR_2PIN 1
9 74HCT138N MUX_2 DIP-16_300MIL 1
10 74ACT04 U1 DIP-14_300MIL 1
11 MC74F74AN U5 DIP14 1
12 1u C1 AXIAL-0.3 1
13 10K R15 AXIAL-0.4 1
15 330 R36,R35,R37 AXIAL-0.4 3
16 S1 LED1 LED-3MM/2.54 1
17 S2 LED2 LED-3MM/2.54 1
18 S3 LED3 LED-3MM/2.54 1
19 100nf C9,C4,C2,C6,C7,C8,C3,C5 RAD-0.1 8
20 1k R7,R16,R30,R31,R32,R33,R10,R8 AXIAL-0.4 8
21 2k R1 AXIAL-0.4 1
22 Header I2C HDR-3X1/2.54 1
23 Header-Female-2.54_2x30 P1 HDR-30X2/2.54 1
24 4k7 R20,R12 AXIAL-0.4 2
25 M05PTH SA,SB 1X05 2
26 Header-Male-2.54_1x8 SDCARD,SPI 210S-1X8P 2
27 74LS670N REG_1,REG_2 DIL16 2
28 SN74HCT175N U2-175,SPI-OUT DIP16 2
29 SST39SF040-70-4I-NHEDIP36-X FLASH DIP-32-600-ELL 1
30 AS6C4008-55PCN SRAM DIP-32-600-ELL 1
31 74AHCT139N MUX_1 DIL16 1
32 Z80CTC-P CTC DIP-28 1
33 CTC_CFG P4 210S-1X8P 1
34 DS1307+ U6 DIP-8 1
35 1825190-3 SW2 SW-TH_8P-L10.2-W7.6-P2.54 1
36 2N5551 Q1,Q2 TO-92(TO-92-3) 2
37 2k2 R3,R18,R34,R2 AXIAL-0.4 4
38 MC74ACT541ANG U4-541 DIP20 1
39 74ACT32 U3-7432 DIP14 1
40 32.768KHz X1 CRYSTAL_TC26V 1
41 CR2032-BS-5-1 B1 VBH2032-1 1


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