Simple Z80 SBC

An originally simple Z80 design to re-create my youth back in the 70s/early 80s. This single board includes all the basics and a few luxuries. To go a little further there are two additional cards: A [VGA character based video card](https://oshwlab.com/peterw8102/8bit-video-card) and a [I/O card providing sound, joystick and generic parallel ports](https://oshwlab.com/peterw8102/z80-pio-keyboard-sound). **NOTE 1** EasyEDA shows the most recent WIP for this project\, which might be part way through me making changes\. Before using the PCB layout please do get in touch \(comment or message\) so I can let you know if what you're seeing is stable\! I create labelled versions of the project\, but EasyEDA doesn't allow me to publish a specific version :\-\( **NOTE 2** The BOM below is automatically generated by EasyEDA but doesn't seem to update properly. Example: U7 (74HCT175) is missing. For an accurate BOM open the the project in EasyEDA and access the BOM from there. **Software is** [available in a related GitHub repo](https://github.com/peterw8102/Z80-Retro)**. As with the board, the software is a work in progress! There's a lot of information on** [how to programme the board in the Wiki](https://github.com/peterw8102/Z80-Retro/wiki)**.** Please do post comments down below if you find any of this interesting, I'd love to share thoughts on how this could be improved in future! I've noticed a few people have cloned it and a few have starred so I'd love to hear from you all. The board has many more options than it really needs so that I can experiment. All devices are through-hole to make the build easy for those of us yet to venture into SMD. Influences for this project include the RC2014 512K RAM/Flash card and the SIO/2 card along with bits and pieces from all over the Internet that I've managed to lose track of. The paged memory model supports a 4MB address space, 1MB of which is used on board. The main header exports all Z80 control lines plus the extended address bus allowing 3MB external. There's a [memory mapped video card](https://oshwlab.com/peterw8102/8bit-video-card) along the lines of the 70s/early 80s systems which sits in the paged memory map. Great for simple games! The board uses an oscillator chip and an optional divide by 2 to the CPU and SIO. This allows a certain level of experimentation with clock speeds. I'm using a 10MHz Z80/SIO/CTC and on the board a 14.74MHz clock which seems to work fine with the parts I have. You can obviously clock this slower if you like. There are jumpers to divide down the 14MHx clock by two or just use a different speed oscillator. Note that changing the processor clock, when using the built in software, will change the serial port baud rate. With the CTC it's possible to decouple the system clock from the SIO baud rate so it's easier to play with clock speeds (although this is not yet supported by the software). Version 2 board features: * 512K SRAM + 512K Flash memory in 16K pages and 4M address range * SIO/0 dual UART * Z80 CTC * SD Card interface. Pins suitable for the breakout board I have. * (2.2) second SD Card interface. Allows two cards but more importantly easy copying between them for cloning. The second connector could also be used for any SPI peripheral with suitable software. * Exported SPI interface. Includes two spare device select lines, also exported, allowing connection to external SPI devices * DS1704+ real time clock with battery backup * i2c interface (used for the clock and available on headers to connect external devices) * 60 pin expansion connector ## Software The banked memory system means there's plenty of space. I have CP/M 2.2 running from SD Card and a boot loader that supports a range of functions including booting from a Raspberry Pi over the second serial port, or booting directly from SD Card. The software is a work in progress but you can [see where I am in the public GitHub project](https://github.com/peterw8102/Z80-Retro/wiki). ## Change Log version 2.2 **Bug fixes from the version 2.1 board:** * The CPU "WAIT" should be pulled high. It wasn't on version 1 and caused no problem (luck I think!) but should be. There are spare resistors in RP1 so a link to one of those fixes this potential issue. * BRDM should be (/MREQ OR BA21),it's incorrectly (/WR OR BA21). Also the second input to BR21SEL should be /MREQ not /WR. Patch for version 2.1: remove BR21SEL jumper and connect the centre pin the MREQ. This limits the addressable memory range to 2M (1 external) rather than 4 but is OK. * Silkscreen error: mux_2 *should* be a 74HCT138, *NOT* 139!! **Enhancements:** * Shrink board size a bit. This reduces build costs for the board. Current WIP 2.2 is 20% smaller in area than 2.1 * Add connector for a second SD Card to allow card-to-card copies * Extend output port 64h to 8 bits. Upper 8 bits select a further 4 SPI devices. Allows efficient access to the second SD card and other SPI devices and minimises changes to SD card library. * Change oscilator layout to accept both 8 bit and 14pin layouts. All my 7MHz parts are 14 pin and my 14MHz parts are 8 :/ * The CR2032 battery holder I used seems to have availability issues. Change layout to accept several different layouts. * Not everyone is going to want a CTC so should be able to leave that out. If you do that then really you want to bridge IO_1 to IOUT to allow the interrupt chain to be maintained on external cards. Add a jumper between these two. (New jumper P5) * Allow SIO - port B to be driven from the CTC or CLKU. 2.1 it was only driven by CLK, the CPU frequency. * Allow SIO - port A to be driven either from the CTC or from CLKU. 2.1 allowed only CLKU and not the CTC for port A. * Include option (link) to divide SIO port A Tx to 3V rather than 5. This would allow direct connect to 3.3V devices. There are some serial to Bluetooth adaptors this would be useful for. * Add support for BOTH SIO/0 (current design) and SIO/2 which seems more popular if less available. Only three pins change function. * Add a "RESET IN" signal on the connector to allow an external system (eg Raspberry Pi) to force a hardware reset. This with a Bluetooth serial adapter would allow completely remote devevlopment. # Changelog 2.1 **Bug fixes:** * Fix layout for 74HCT04 - Incorrect 16 pin package used. Replaced with correct 14 pin package. * Pull up control lines (INT and others) - missing ulls ups result in unpredicatably behaviour. **Changes from version 1 to version 2** * Add SPI interface * Add i2c interface * Add i2c real time battery backed clock (DS1307+ chip) * Add SDCard hardware interface (single card) * Add optional clock divider - selected by jumper. Select either full oscillator speed or 1/2. * Add Z80 CTC * Remove LED bar. Required too much logic to drive. ## Comments/thoughts With the SDcard interface working very nicely maybe the board doesn't need 512K of flash. It's a complete PITA to programme compared with simply writing to the SD card. Maybe a smaller flash device?