© 2024 EasyEDA Some rights reserved ISO/IEC
1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
4.For enterprises, more professional users
STD test
Mode:
All simulation schematics MUST have a ground 01
Open in EditorEasyEDA switches are not ideal
Open in EditorControlling EasyEDA switches
Open in EditorSpice PULSE Source
Open in EditorCrystal oscillator using EasyEDA quick starting crystal spice model
Open in Editorswitch test
Open in EditorProbing currents 01
Open in EditorProbing currents 01
Open in EditorParameters, expressions, functions and B Sources
Open in EditorNets can be joined by netnames 01
Open in EditorNets can be joined by netnames 02
Open in EditorNets can be joined by netnames 03
Open in EditorProbing voltages 01
Open in EditorID | Designator | Quantity |
---|---|---|
1 | V1 | 1 |
2 | R3,R2,R1 | 3 |
3 | A1,A2,A3 | 3 |
4 | R1,RLOAD2,RLOAD3,RLOAD1,RLOAD4,RLOAD5,RDC_PATH_TO_GROUND,R3 | 8 |
5 | VIMON1 | 1 |
6 | B1 | 1 |
7 | R4 | 1 |
8 | H1 | 1 |
9 | F1 | 1 |
10 | R5 | 1 |
11 | B2 | 1 |
12 | S1,S4 | 2 |
13 | W1,W2 | 2 |
14 | R_SW_TOPEN | 1 |
15 | R_SW_TCLOSE | 1 |
16 | V1 | 1 |
17 | V2 | 1 |
18 | F1 | 1 |
19 | VM1,VM2 | 2 |
20 | V1 | 1 |
21 | S3 | 1 |
22 | S1 | 1 |
23 | V1 | 1 |
24 | C1 | 1 |
25 | C2,C1 | 2 |
26 | V2 | 1 |
27 | ROUT | 1 |
28 | BINVERTER | 1 |
29 | RFB | 1 |
30 | QXTAL1 | 1 |
31 | RSER | 1 |
32 | S1 | 1 |
33 | V1 | 1 |
34 | C1 | 1 |
35 | R3,R4 | 2 |
36 | B_BLN1 | 1 |
37 | B_IDEALV1 | 1 |
38 | B1 | 1 |
39 | B_THEV1 | 1 |
40 | RSER1,RPAR1,RPAR2 | 3 |
41 | CPAR1,CPAR2 | 2 |
42 | B_FUNC1 | 1 |
43 | B5 | 1 |
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