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STD 6502 Single Board Computer
Mode:
6502 based SBC Most of the design from Grant searle original design.
The original circuit was produced by Pennuto73, thanks for the orignal work.
I have Added a jumper to allow 256k ROM giving access to two pages of ROM with a single jumper, also
re-connected the RTS line to aid with hardware connection to a PC.
I also had issues with getting the Xtal to work with the LS series, so I adjusted the 2k2 resistors and switched to
using HCT series. In theory this would also hel with using a 65c02 chip.
The circuit layout was created by me with improved silk screen markings to help make sure things like the FTDI are connected the right way!
ID | Name | Designator | Footprint | Quantity | |
---|---|---|---|---|---|
1 | A14 | J4 | HDR-TH_3P-P2.54-V-F-4 | 1 | C18164975 |
2 | A15 | J5 | HDR-TH_3P-P2.54-V-F-4 | 1 | C18164975 |
3 | RESET | SW1 | TACTILE-PTH-EZ CZ | 1 | |
4 | POWER | D1 | LED-TH_BD3.0-P2.54-RD | 1 | |
5 | NE555 | U1 | PDIP-8_L9.6-W6.4-P2.54-LS7.9-BL-1 | 1 | C2859604 |
6 | 100n | C9,C3,C4,C5,C6,C7,C8 | C1 | 7 | |
7 | 10u | C10,C1 | CAP-D6.3-F2.5 | 2 | |
8 | 47k | R10 | R3 | 1 | |
9 | 1M | R1 | R3 | 1 | |
10 | 27128/512 | U4 | DIP28-600 | 1 | |
11 | 6502CPU | U5 | PDIP-40 | 1 | |
12 | 10k | R2,R3 | R3 | 2 | |
13 | 2K2 | R5,R6,R7 | R3 | 3 | |
14 | 270P | C2 | C1 | 1 | |
15 | FTDI | H1 | HEADER 1X6 | 1 | |
16 | USB POWER | J1 | 1X2 PIN HEADER 2.54MM | 1 | |
17 | Header-Male-2.54_2x18 | P1 | HEADER-MALE-2.54_2X18 | 1 | E50980 |
18 | 62256P | U2 | DIP28-600 | 1 | |
19 | 6850 | U3 | DIP24-600 | 1 | |
20 | 1.8432MHz | X1 | HC-49S | 1 | |
21 | 74LS00 | U6 | DIP14 | 1 | |
22 | 74LS04 | U7 | DIP14 | 1 |
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