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2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
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2.Smooth support for design sizes of over 30,000 devices or 100,000 pads
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STD 21d CPU and Clock
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Description
Z80 CPU + Clock
RC2014 compliant
Design Drawing
schematic diagram
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PCB
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| ID | Name | Designator | Footprint | Quantity | Mounted | |
|---|---|---|---|---|---|---|
| 1 | 2.54mm 1x40P | RC40_BUS | HDR-2.54-Z-1X40P | 1 | Yes | C2337 |
| 2 | 2.54mm 1*10P Straight Female header Gold-plated | EXT_BUS | HDR-10X1/2.54 | 1 | Yes | C35445 |
| 3 | 10K | R3,R2,R4,R1,R5 | AXIAL-0.3 | 5 | Yes | |
| 4 | Z80CPU | IC1 | DIP40 | 1 | Yes | |
| 5 | 100nf | C2,C1 | RAD-0.1 | 2 | Yes | |
| 6 | 1M | R6 | AXIAL-0.3 | 1 | Yes | |
| 7 | 1k | R7 | AXIAL-0.3 | 1 | Yes | |
| 8 | 22pF | C3,C4 | RAD-0.1 | 2 | Yes | |
| 9 | 49S | X1 | HC-49S | 1 | No | |
| 10 | 74HCT04N | U1 | DIP14 | 1 | Yes | |
| 11 | JUMPER_2p | JP1,JP2 | 1X02 | 2 | Yes |
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