Project Description

The original intention is to participate in the electric competition, Taobao a lot of ZYNQ ADC DAC DDS PL are more expensive, and the quality is not good, after participating in the electric competition in the summer vacation and getting the national one, it has accumulated a lot of modules such as 170MSPSADC, 210MSPSDAC, 1.6GSPS 16bit DAC, 9GHz PLL, 500MSPS 12bit ADC and other modules, and recently successfully made the core board of the ZYNQ7020, (I don't see ZYNQ7020 open source on oshwhub), all kinds of modules and ZYNQ are cheap, sufficient, and good performance as the goal, and all of them are open source while the Spark plan is being organized! (PS: this is just the beginning).

This project brings you the minimum cost of only 90 yuan ZYNQ7020 core board! (A certain zynq7020 chip 45.4 yuan, PCB JLC free 6-layer board template, really sweet)  

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Open-source protocol

Commercial use is prohibited without the permission of the author. Reprinting or citation should indicate the original author and the link to the project

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Project-related Features

Resource Introduction:

(1) ZYNQ7020/7010 core board: 1 DDR3, QSPI FLASH, SD card adapter chip, UART serial port to USB, PS clock 33.3333Mhz (not recommended to change the frequency), PL clock 50Mhz (can replace other frequencies by yourself). There is also 1 USER LED (L14) and 1 RGBLED (T16). The PL resource is 66 (33 pairs) of differential equal-length IOs, and the default voltage is 3.3V.

(2) 170MSPS 12bit ADC: Based on Linear LTC2220, the maximum sampling rate can reach 170M, 12bit. The analog front end is a ADA4937 ultra-low distortion differential ADC driver with a -3dB bandwidth of 1.9GHz. The input impedance is 50Ω and the gain is 2 (can be changed by yourself). On-board power management with ultra-low noise ultra-high PSRRLDO and through-center capacitor filtering with a 5V 2510 interface input.

(3) 210MSPS 14bit DAC: Based on ADI AD9744, the maximum sampling rate can reach 210M, 14bit. The backend is ADA4891 or TPH2501. The gain is self-changeable, with a bandwidth of 50Mhz, an output amplitude of ±2.5V, and an output impedance of 50Ω. On-board power management, analog and digital power supply for the DAC using ultra-low noise ultra-high PSRR LDO, on-board single-turn positive and negative voltage module, which can output ± 2.5V, and use penetrating capacitor filtering, the input is a single 5V 2510 interface.

(4) 9.8GHz wideband PLL with integrated VCO: Based on TI LMX2592, the output frequency range is 20Mhz-9.8Ghz, supports fractional N and integer N modes, and has a 32-bit fractional divider to support the selection of appropriate frequency. Programmable phase adjustment, programmable charge pump current, programmable output power level. Dual-channel output with 50Ω output impedance. An on-board temperature-compensated crystal reference source or an external reference input can be locked with input clock frequencies up to 1400MHz. On-board power management with ultra-low noise ultra-high PSRRLDO and through-center capacitor filtering with a 5V 2510 interface input.

(5) 500MSPS 12bit ADC: Based on ADI AD9434, the maximum sampling rate can reach 500M (DDR) and 12bit. The analog front end is a LMH6521 high-performance dual-channel DVGA with a -3dB bandwidth of 1.2Ghz. The input impedance is 50Ω, the programmable gain, the dynamic range is 31.5dB, and the step size is 0.5dB. The interface uses 1.8V LVDS. On-board power management, using an integrated DCDC and ultra-low noise ultra-high PSRRLDO, with through-center capacitor filtering, and an input of 5V 2510 interface.

(6) 1600MSPS 16bit DAC: Based on ADI AD9142, the maximum sampling rate can reach 1.6G (DDR) and 16bit. Dual-channel output, built-in NCO, quadrature modulator, phase-locked loop. The interface uses 1.8V LVDS. On-board power management, using an integrated DCDC and ultra-low noise ultra-high PSRRLDO, with through-center capacitor filtering, and an input of 5V 2510 interface.

Project Properties

This project is the first public and is my original project. The project has not won an award in another competition.

Project Progress

1. ZYNQ7020 Core Board:

(1) ZYNQ chip: normal work, VIVADO normal connection:

(2) Onboard UART to USB: works normally, print HELLO.

(3) DRAM DDR3 test: working normally, 0 errors:

(4) Program curing test: normal curing, normal starting:

At this point, the ZYNQ7020 core board is completely overtested and can be used normally.

(2) Each RF module:

(1) 170MSPS 12bit ADC: Normal operation As shown in the figure, the waveform of the 10Mhz signal is acquired, and the SNR can reach 61.3dB.

(2) 210MSPS 14bit DAC: Normal operation As shown in the figure, the output baseband signal is a 100% AM modulation signal of a triangle wave.

(3) 9.8GHz wideband PLL with integrated VCO: normal operation As shown in the figure, the output is 7Ghz.

(4) 500MSPS 12bit ADC: Normal operation As shown in the figure, the sampled signal is used.

(5) 1600MSPS 16bit DAC: Normal operation

Design Description

1. ZYNQ7020 core board:

(1) Power supply part: The power supply adopts a DCDC converter with TPS82130 integrated inductor, and the maximum output current is 3A. Four power supplies, the voltages are 1.0V, 1.5V, 1.8V, 3.3V, and the output is filtered by a penetrating capacitor. The input is 5V, and the power-up sequence is 1.0→1.8→1.5→3.3.

(2) DDR3: DDR3 uses Micron's monolithic MT41K256M16.

(3) FLASH: QSPI FLASH adopts W25Q256JVEIQ(or W25Q128JVEIQ)

(4) SD card adapter: The SD card adapter uses TI's TXS02612RTWR.

(5) Clock: PS adopts 33.3333MHZ 20ppm active crystal oscillator, PL adopts 50Mhz 20ppm active crystal oscillator.

(6) UART to USB: Adopt the CH343p chip of domestic WCH, support automatic recognition and dynamic self-adaptation of communication baud rate of 115200bps and below.

(7) USER LED: L14 is linked to a 0603 monochrome LED, and T16 is connected to WS2812b RGBLED (see attachment for driver).

(8) Board-to-board connector IO resources: PL resources are 66 (33 pairs) of differential equal-length IOs, and the default voltage is 3.3V. The PS side leads to the SD card and JTAG, and the rest of the pins can be implemented through EMIO using PL pin resources if necessary.

(9) Boot mode selection: There are three boot modes, namely JTAG boot, QSPI FLASH boot, and SD card boot. Changes can be made via the DIP switch on the core board:                                                  

(10) ZYNQ chip model: xc7z020-1clg400, xc7z020-2clg400, xc7z010-1clg400, xc7z010-2clg400.

Software Description

(1) The driver engineering of the LTC2220 AD9744 LMX2592 given in the ZYNQ7020 part is shown in the attachment, and the VIVADO version is version 2022.1.

(2) The driver engineering of AD9434 is zynq7035 (see my 2023 National Competition D open source project for the adapter board), see the attachment, and the VIVADO version is version 2022.1.

(3) The driver engineering of the AD9142 is zynq Ultrasale + MPSOC XCZU3EG (the interface definition is the same as that of the AD9434), see the attachment, and the VIVADO version is version 2022.1.

Physical Display

Design Considerations

(1) When soldering the Zynq core board, it is recommended to solder the power supply now, test the normal power supply voltage, and then solder the penetrating capacitor and other chips after the starting sequence is normal, so as to prevent the chip from being damaged due to abnormal power supply.

(2) When soldering zynq chip (BGA) and DDR3 (BGA), my welding method is to remove the nozzle at the front end of the air gun, 370 degrees, wind speed 3.5 bars, about 2-3 minutes, the zynq chip can be slightly pushed with tweezers, and the welding is completed when the Q bomb is felt. (Do not toggle in large sizes, it will cause a short circuit in the BGA pad!!) ）

(3) Suggestions for soldering sequence: power supply - BGA chip - front peripheral circuit - reverse capacitor resistance - each connector.

(4) Suggestions for welding methods: In addition to the BGA chip on the front, I soldered through the heating table (see my portable heating table open source project), and the BGA chip and the reverse face resistance were welded by air guns.

(5) After the welding is completed, it can be verified by the ZYNQ+RGBLED test program in the programming attachment.

(6) The IO of the PL terminal of the core board is a differential equal-length lead-out, and the default BANK voltage is 3.3V, which can be changed by yourself if necessary.

(7) There is a 0603 resistor bit (R83) behind the core board and typec, and this resistor selects whether to supply power through the typec interface, if not, do not solder.

Description of project Attachments:

(1) The attached is a demonstration video of the ZYNQ7020 core board launching the RGBLED test program from the onboard QSPI FLASH.

(2) Due to the 50M upload limit, detailed test and demonstration videos will be posted on the core board ZYNQ7020 [open source] of station B and various ADDA RF modules.

(3) Test procedures for each module: ZYNQ7020 and various module test procedures. pwd: 55xj (Baidu network disk)