I created a simple schematic with parts from the common library [component details unimportant]:

• a 2-pin connector
• a resistor

I exported this to a 4-layer board:

with this setup:

[There's a bug that automatically assigns the pour on the VCC layer to net GND; I manually corrected that.]

This autoroutes as expected, two tracks on the top layer:

But ...

I don't want to clutter the top signal layer with GND and VCC tracks. It's the whole reason that I created those inner planes.

So I created blind via types in DRC: TV is top to VCC, and TG is top to GND:

Then I drop vias next to the GND and VCC pins of R1, change their nets appropriately, and convert them to the appropriate blind vias.

At this point, there are ratlines from R1's pads to the blind vias, as I guess I expected:

Problem 1: Autorouting this to draw the two tiny tracks from R1 to the vias hangs forever [ok... until I run out of patience minutes later...].

Problem 2: If I manually route those two tracks:

[note that the ratlines went away, as expected], and autoroute [i.e., to autoroute the other components that I'd also add in a real project], it finishes, but it redraws the same two now-redundant tracks across the signal layer as before, even though they are not needed [or wanted]:

Why?  Can I avoid this? It's why I put in the planes and vias in in the first place: to avoid hogging real estate and setting myself up for failed routing on the top layer.

Thanks!

...R