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STD Configuring AC Sources 01

Configuring AC Sources 01

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Update time: 2019-11-09 16:47:21
Creation time: 2018-03-21 11:20:19
Description

Description

This simulation shows how the AC Source part of the Independent Voltage (and Current) source can be configured for use in AC Analyses. The example shows how more than one AC Source can be configured in a circuit to represent different signal sources at the same frequency but with different phases. The example also shows how the phase settings relate to the same signals in the time domain. In this example both AC Sources are set to the same amplitude of 1. They could be set to different amplitudes: try it and compare the results with the same amplitude changes in the time domain part of the signal sources. Note, however, that the AC Analysis assumes that the circuit is perfectly linear so even if an AC Source amplitude 100 were to be specified, the output would still look as if it came from a perfectly linear circuit. Compare that with what happens if the time domain parts of the sources are set to 100! This is what the circuit is doing: Vinphase drives the capacitive end of the single stage allpass RC network of R1 and C1. C1 therefore decouples (removes) the DC offset of V(inphase) at the R1C1 node. Vinphase also drives the base of Q1 which forms a single transistor phase-splitter stage. V(Q1E) is nominally the same as V(inphase) but offset by the Vbe drop of Q1. The emitter of Q1 drives the capacitive end of the single stage allpass RC network of R2 and C2. C2 therefore decouples (removes) the DC offset of V(Q1E) at the R1C1 node. The collector of Q1 drives the resistive end of the single stage allpass RC network of R2 and C2. The small difference in the values of RQ1E and RQ1C are to compensate for the fact that the collector circuit gain is approximately 1/(Q1 current gain) times lower than the emitter circuit gain (because the emitter circuit contains the additional contribution of the base current). The inherent DC offset of V(Q1C) appears at R2C2 but is removed by the highpass filter formed by C4 and R4. The cutoff frequency of this filter is so far below that of the band of interest that the effect of the filter at AC can be ignored. The highpass filtered output appears at the outbjt node. Voutofphase drives the resistive end of the single stage allpass RC network of R1 and C1. To ensure that the circuits are, as near as possible equivalent, the output from R1C1 is also passed through an identical highpass filter, R3 and R3 before being measured at the outideal node. Running the transient Analysis shows that the outputs are almost identical. The small differences are because: i) Q1 does not have exactly +1 gain at the emitter or -1 gain at the collector. The gains are very slightly less than unity because of the finite current gain of Q1. ii) Q1 has some parasitic capacitances that will contribute a very small error to the phase shift. In the time domain: Vinphase is a SINE source configured to generate a time domain output of a 1V pk-pk 1kHz sinewave (i.e. 0 degrees phase shift) with a 4V DC offset. Voutofphase is a SINE source configured to generate a time domain output of a 1V pk-pk 1kHz inverted sinewave (i.e. 180 degrees phase shift) with a 0V DC offset. Running the Transient Analysis shows that the outputs are almost identical. In the frequency domain: Vinphase is an AC source configured to generate a frequency domain output of amplitude 1 with 0 degrees phase shift and a 4V DC offset (due to the DC offset of the time domain Source which in an AC Analysis is simply treated as a DC source). Voutofphase is an AC source configured to generate a frequency domain output of amplitude 1 with 180 degrees phase shift and a 0V DC offset. Running the AC Analysis shows that the outputs are almost identical. The small differences between the ideal and bjt results in both the Transient and the AC Analysis results are because: ` i) Q1 does not have exactly +1 gain at the emitter or -1 gain at the collector. The gains are very slightly less than unity because of the finite current gain of Q1. ii) Q1 has some parasitic capacitances that will contribute a very small error to the phase shift.
Design Drawing

Design Drawing

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ID Name Designator Footprint Quantity
1 SIN(0 1 1k 0 0 180) AC 1 180 VOUTOFPHASE 2P-5.0 1
2 SIN(4 1 1k 0 0 0) AC 1 0 VINPHASE 2P-5.0 1
3 9 VCC 2P-5.0 1
4 1k R1,R2,RQ1E R3 3
5 1G R3,R4 R3 2
6 1u C1,C2 1206 2
7 1 C3,C4 1206 2
8 2N3904 Q1 SOT23 1
9 1.0499k RQ1C R3 1

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