1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 30,000 devices or 100,000 pads
3.More rigorous design constraints, more standardized processes
4.For enterprises, more professional users
Std EditionUberclamp simulation
License: CC-BY-NC-SA 3.0
This project contains several simulation schematics for the EasyEDA Uberclamp Overvoltage Protection Circuit.
It was originally conceived as a reverse input polarity protected, fast, self-resetting, current limited, overvoltage protector or Computer Saver for the Commodore C64 computer.
The original schematics were imported into EasyEDA from LTspice .asc files and have been edited to remove the models (as they are already in the EasyEDA libraries), change reference designators, netnames and add descriptive information where applicable.
There are simulations of variants of the complete circuit and of individual sections of the complete circuit.
Uberclamp final circuit is the simulation schematic from which the non-simulation schematic is derived and from which the PCB is designed.
The original simulation schematic was imported from LTspice and has been lightly edited to run in EasyEDA. The required changes are detailed in the versions of the schematcs.
The various models and subckts required to run this simulation are all in the EasyEDA spice library.
What is Uberclamp?
Uberclamp is a precision overvoltage protection clamp with output overcurrent limiting and input reverse polarity protection.
Unlike some other overvoltage protection schemes, Uberclamp is completely solid state: it contains no fuses or electromechanical relays.
Simply by the choice of which components are fitted to the PCB, the design supports three basic versions of the protection behaviour:
1) Latched timeout
For an input overvoltage and/or output overcurrent event of longer than a preset timeout interval, the load is disconnected from the input supply and remains so until the input supply is disconnected and reconnected.
This functionality is achieved with the basic circuit.
2) Automatic reset
For an input overvoltage and/or output overcurrent event of longer than a preset timeout interval, the load is disconnected from the input supply until after a second time interval, when the latching function is reset. If the fault conditions persist then the protection and automatic reset cycle will repeat until the end of the automatic reset cycle during which the fault conditions are removed or the input supply to the protection circuit is disconnected.
This additional functionality is achieved by fitting a dual opamp (U3), two transistors (Q6, Q7), three diodes (D5 - D7), seven resistors (R19 - R27) and two capacitors (C8, C9) to the basic circuit.
3) Input reverse polarity protection
Operation of the circuit is the same as for version (2) but with the addition of input reverse polarity protection using a so-called “ideal diode”.
This additional functionality is achieved by fitting a second P channel MOSFET (M1) (of the same type as that used in the main circuit) plus - depending on the choice of opamp and certain capacitor voltage ratings and hence the permissible maximum input voltage range - an optional zener diode (D2) and one resistor (R10).
If these components are not fitted then a wire link has to be soldered from the Drain pad to the Source pad M1.
Note that functions of Uberclamp could more simply be realised using the LT4356 or LTC4364 series of devices from Linear Technology but it was decided to design a more DIYable and hobbyist friendly circuit using readily available and easily assembled components.
Note in particular that the footprints for M1 and M2 have plated though holes to allow hand soldering of the tab from the back of the PCB and to provide a solder heat slug
How and why was Uberclamp developed?
The impetus to develop a power supply overvoltage protection circuit came from a chance conversation at York Hackspace about the output overvoltage fault exhibited by some of the original power supply units for the Commodore C64 computer.
Uberclamp is the result of several months investigation, conversations with a couple of people in the Lemon64 community, simulations and development through a number of different overvoltage and overcurrent protection schemes, including shunt clamping, fast series disconnection using a MOSFET, constant current and foldback current limiting and timed fault latching.
There are some overvoltage protection devices available that use an electronic overvoltage detection circuit to then open an electromechanical relay to disconnect the load. Such devices are too slow to guarantee protection of the components in the load against supply voltage increases of above their Absolute maximum voltage ratings for input overvoltage rates of change of faster than about 0.13V/ms.
The Relay timings and MOSFET vs relay switching times simulations in the following EasyEDA project demonstrates this:
Furthermore, to protect against false disconnections due to transients in the incoming supply, these devices often have a delay built in to prevent the relay opening for transient overvoltages of less than a certain time interval. This allows an overvoltage event to be applied to the load for at least this delay interval even before power to the relay coil is removed.
The use of a solid state parallel clamp or shunt regulator has been investigated and shown to be at least two orders of magnitude faster than a relay based series disconnecting switch.
The simulations in the following EasyEDA project demonstrates this:
To prevent the shunt element dissipating significant power for a prolonged overvoltage event, some form of fuse protection is required.
The problem with this is that if the source cannot supply a big enough margin between the load current and the current that is required to blow the fuse then the fuse never blows and the shunt element is left still dissipating significant power for the entire duration of the overvoltage event.
However, if there is sufficient margin between the load and the maximum current available during an overvoltage event then because the time delay of the fuse blowing is only crudely selectable by fuse type, there is the risk that a transient overvoltage event may blow the fuse.
A simple crowbar circuit based on a thyristor suffers the same basic problems as the shunt clamp except that a crowbar offers no short term overvoltage clamping. Once an overvoltage has been detected - with or without any time delay - the thyristor is turned on and stays on until either the series protection fuse blows or the input voltage is removed. Particularly at low supply voltages where the thyristor ON voltage may be a significant proportion of the normal supply voltage, it is not certain that the thyristor dissipates less power that the shunt camp since the clamp only sinks the excess (available source minus the load) current whereas the thyristor may sink almost the total available source current because the load may take negligible current at supply voltages much less than the rated voltage. For example, most CMOS devices draw almost no current once their supplies drop below their rated minimum operating voltages.
Replacing the electromechanical relay with a MOSFET as the series disconnection element is possible and removes the problem of the time delay for the relay to open because the MOSFET operates orders of magnitude faster than the relay and so can protect against excessive voltage rise across the load for input voltage rates of change of the order of 27.3V/ms.
The MOSFET vs relay switching times simulations in the following EasyEDA project demonstrates this:
However there is still the problem that any delay used to filter out transient overvoltages to prevent spurious load disconnections can still apply voltages to the load that can exceed the Absolute Maximum Voltage ratings of components in the load if the rates of change and voltages are big enough.
Using a very low dropout voltage (i.e. the minimum input to output voltage difference for proper operation) linear regulator so that the output voltage can be regulated to just below the required value is possible but such devices rarely have dropout voltages of less than about 300mV which for many applications is too much.
The operation of linear regulators is not normally well specified for input to output voltages of less than the dropout voltage so it is not clear how the output will behave if such devices are set to regulate to an output voltage of just below the Absolute Maximum Voltage ratings of components in the load but then are operated below that voltage plus the dropout voltage. For a rising input voltage the speed with which they come into regulation and the associated output overshoot may also be poorly specified.
It is possible however to design a dedicated low dropout linear regulator where the series pass element simply presents a very low insertion resistance until the input voltage reaches the required regulated output voltage. At input voltages above this voltage, the output is then regulated at the required output voltage. With careful design this type of circuit can be made to have a fast, predictable response at the onset of and during regulation and as regulation is lost as the input falls below the regulated level and the series element returns to just presenting a low resistance.
Of the solutions described so far only the low dropout regulator may intrinsically offer any form of built-in current limiting or power dissipation based thermal overload protection to protect against prolonged exposure to an input overvoltage or output overcurrent fault condition.
With a relay of inadequately rated carrying current, an output overcurrent fault may fuse the relay contacts shut. Adequately rating the relay then throws the overcurrent problem back into the wiring and PCB traces that connect the supply to and from the working contacts.
Whilst a shunt clamp is inherently short circuit protected, the rest of the circuit supplying it, in particular the wiring and PCB traces, may not be.
A series MOSFET may be adequately rated to withstand the maximum short circuit load current but unless the gate-source voltage is maintained in a short circuit condition, i.e. the input supply voltage holds up with the excessive load current - which is especially a problem when using P channel MOSFETs - the device may drop out of hard turn-on (with very low on-resistance and hence power dissipation) and so will start dissipating significant power.
The basic constant current limiting function of most linear regulators results in high power dissipation in the series pass element.
Foldback current limiting can be used to reduce the power dissipation in the series pass element but can be difficult to implement when connecting to loads such as computer motherboards with a lot of decoupling capacitance. The initial current required to charge the supply decoupling may be high enough to put the protection into current foldback at switch-on so there is never enough current to charge up the load capacitance so the supply rail never comes up.
Hence for a series MOSFET disconnection or a low dropout linear regulation based scheme, either adequate heatsinking, some form of thermal monitoring or a timer to switch the series device off before it gets too hot will be required.
There is also the question of what to do after a fault has occurred and it is then removed.
There are two fault situations to be recovered from:
i) an input overvoltage;
ii) an output overcurrent
The recovery options are:
a) user intervention, i.e. disconnect/reconnect the input supply or the pressing of some sort or reset button;
b) automatic reset where the circuit periodically tries to reconnect power to the load but reasserts the protection if the fault is still present.
Some series disconnection schemes automatically reconnect the load. Some latch the series element in the open circuit or off state and then require some user intervention such as removing and reconnecting the input supply or pressing a manual reset button.
In a simple series disconnect circuit the series element an automatically reconnect the input to the load once the input voltage has dropped below some predefined trip level. This level may be the same as the overvoltage disconnection voltage or slightly below it to reduce “fizzing” - very fast switching on and off - around the trip point. In most applications, the sudden removal of the load current will make the input voltage rise anyway so this reduction on trip level may not be necessary.
Clearly, an automatic timed reset can not be used in such circuits because the reset would temporarily connect the input voltage - which since the load has been disconnected because there’s an overvoltage fault - would connect an overvoltage straight to the load.
If a suitable low dropout regulator device could be identified then recovery from an output overcurrent fault may simply require the user to wait for the inbuilt thermal protection to allow the device to cool down enough for it to start operating again.
In series disconnection schemes without active current limiting circuitry, the series protection fuse would usually have to be replaced.
The shunt clamp element itself requires no user intervention as it simply turns off when the overvoltage is removed however, except for the case without fuse protection, the series protection fuse would have to be replaced.
If a suitable low dropout regulator device could be identified then recovery from an output overcurrent fault may simply require the user to wait for the inbuilt thermal protection to allow the device to cool down enough for it to start operating again.
What makes Uberclamp better than other options?
The design used in Uberclamp combines the best elements of the options described above:
a fast turn-on low (in fact zero) dropout linear regulator;
a fast series disconnect overvoltage protection switch;
constant current limiting;
automatic delayed disconnect;
latched protection state;
automatic timed reset
The end result is a circuit which, using a MOSFET, acts as a low insertion resistance series switch for any input voltage below an accurately defined and stable overvoltage CLAMP voltage whilst for an input voltage above the CLAMP voltage, acts as a linear regulator. In either mode of operation, the output is current limited and to limit power dissipation in the series MOSFET switch element, the switch is latched in an open circuit state after a defined and stable timeout period.
For an input voltage in the normal range, the insertion resistance of the circuit is dependent on the on resistance of the MOSFETs chosen plus the value of the resistance used to sense the current drawn by the load. For the DMP4015SK3 from Diodes.com the on resistance, excluding connectors and wiring is approximately 15mR. For an STD52P3LLH6 from ST.com the on resistance, excluding connectors and wiring is approximately 20mR. This rises to about 50mR for an OnSemi 2SJ652 and just under 100mR for a Vishay SQ3419EEV.
The current sense resistor is 10mR so using the DMP4015SK3, at a 1A load the voltage drop of the circuit for an input below the CLAMP voltage is about 25mV. A second DMP4015SK3 for the reverse input voltage protection adds another 15mR. Including wiring and connector losses the overall voltage drop at 1A could be expected to be less than 100mV.
With both M1 and M2 fitted, at load current of 1A, the measured total voltage drop across Uberclamp including the connector and PCB copper areas is 45mV. This drop comprises 42mV through the high side path of M1, M2 and the sense resistor plus 3mV through the ground path. At 1A, this equates to a total insertion resistance of 45mR.
For an input voltage above the CLAMP voltage, the circuit initially behaves as a fast series voltage regulator which linearly regulates the output voltage to the CLAMP voltage with negligible overshoot.
If the input voltage drops to less than the CLAMP level before the end of an accurately defined timeout period, the output voltage will drop back to the input voltage less the small insertion voltage drop.
When the circuit operates as a linear voltage regulator, the series MOSFET is clearly no longer operating as a very low resistance switch. Under these conditions, the MOSFET has a significant voltage across it and essentially the same - or in fact a slightly higher - load current drawn through it as prior to the overvoltage fault. The power dissipation in the MOSFET therefore increases significantly over that when it is operating as a low resistance switch.
To limit the temperature rise in the series MOSFET due to this extra power dissipation, for an input voltage that exceeds the CLAMP level for longer than the timeout period, the series MOSFET switch goes open circuit and the output voltage will drop towards zero at a rate determined by the load current and any parallel capacitance.
This load disconnection action is latched. Therefore, in the basic circuit with no automatic reset, the input voltage must be removed and then reconnected - at a voltage lower than the CLAMP level - before the output voltage will be re-applied to the load.
The latching action is reset by shorting the
TIMEOUT net to ground to discharge a capacitor, C7. Therefore it would be possible to reset the latching action by shorting the
TIMEOUT net to ground using a push-button switch but this is not recommended because the length of time for which a manual button press may hold off re-asserting the latching action could allow excessive dissipation in the series MOSFET.
To avoid this problem, a short reset pulse could be generated by a monostable in response to a manual button press but the additional circuit complexity was considered unnecessary since the optional automatic reset feature accomplished the same function more elegantly and without the need to for user intervention.
During normal operation, i.e. with no input overvoltage present, any load current that exceeds an accurately defined and stable ILIMIT level will result in the output exhibiting a constant current limiting action. This causes the output voltage to drop to whatever level is required to maintain a load current equal to the current limit or to zero, whichever is reached first.
For a load current that falls below the ILIMIT level again before the end of the timeout period, the output current limiting is removed and the output voltage will return to the input voltage less the small insertion voltage drop.
When the circuit operates as a constant current limiter, the series MOSFET is clearly no longer operating as a very low resistance switch. Under these conditions, the MOSFET has a significant voltage across it - up to the whole of the input voltage including any overvoltage - and a current equal to the current limit drawn through it. The power dissipation in the MOSFET therefore increases significantly over that when it is operating as a low resistance switch.
To limit the temperature rise in the series MOSFET, for a load current that exceeds the ILIMIT level for longer than the timeout period, the series MOSFET switch goes open circuit and the output voltage will drop towards zero at a rate determined by the load current and any parallel capacitance.
This load disconnection action is latched. Therefore, in the basic circuit with no automatic reset, the input voltage must be removed and then reconnected - at a voltage lower than the CLAMP level and to a load that draws less than ILIMIT - before the output voltage will be re-applied to the load.
In the same way as for the overvoltage protection this latching action could be reset by a manual pushbutton switch but again, to remove the risk of the series switch MOSFET being subject to excessive power dissipation for the duration of a manual button press and to avoid the additional circuitry required to provide a monostable controlled reset pulse, the use of the optional automatic reset circuit is considered the preferred solution.
A second simulation schematic also features an additional circuit (also imported from LTspice) to add a FAULT warning output and an automatic reset timer to reset the latched state if the input voltage is below the CLAMP voltage and the load current is less than ILIMIT.
The FAULT warning output goes high when the series MOSFET is latched off to disconnect the load. Therefore the FAULT output indicates the occurrence of an overvoltage or a current limit fault of a duration longer than the timeout period.
The FAULT warning output goes low as the timeout period is reset by discharging C7 to ground by the automatic reset circuit and, in the continued presence of a fault, will go high again at the end of the timeout period. If the fault condition has been removed by the time the next automatic reset starts, the FAULT warning goes low and stays low until another fault condition arises. The FAULT warning obviously goes low if the input is disconnected and reconnected with no fault conditions present.
While the FAULT warning output is low, a simple interval timing circuit is held disabled. When enabled, this circuit always starts from the beginning of the timer interval.
After rising relatively slowly as defined by the timeout interval, at the point where the MOSFET is latched off, the voltage across C7 rapidly climbs to the input voltage. As this voltage rises to less than about 0.5V below the input voltage, the the FAULT warning output goes high.
When the FAULT warning output goes high, the interval timing circuit is enabled at the start of the timing interval. At the end of the timing interval a transistor is turned on which discharges C7. This turns the MOSFET back on again, resets the timeout interval and also resets the FAULT warning output low which disables the automatic reset timer until the next timeout interval has expired.
If the fault is removed before the next timeout interval expires then the FAULT warning output remains low and the automatic reset timer is held disabled.
How it works
The following is a detailed description of the operation of Uberclamp.
The circuit comprises six main sections.
Reverse polarity input voltage protection is provided using a reverse drain-source connected P channel MOSFET, M1, configured to operate as an ideal diode function. The gate of the M1 is pulled to ground through resistor, R10. With the correct (positive) input voltage polarity, the body diode of M1 conducts and so initially supplies power to the source side of M1. With the source pin being pulled up to one diode drop below the input voltage, this is sufficient to bias M1 fully on with an Rds_on of about 15mR, which then effectively shorts out the forward biased body diode and so presents a very low forward voltage drop between the input supply and the M1S net.
With the incorrect (negative) input voltage polarity, the body diode is reverse biased so M1 is biased off and therefore the input voltage is blocked.
If reverse polarity input voltage protection is not required then M1, R10 and D2 can be omitted and the source and drain pads of M1 shorted together with a wire link.
A 2.5V precision reference (REF2V5) for the high impedance input at pin 2 (VFB) of opamp U2.1, via R9, is provided by the TL431 shunt reference diode, U1.
A potential divider, R14 and R16, from the cathode of U1 supplies a 1.25V reference (REF1V25) to the high impedance input of the PNP emitter follower buffer, Q4.
U1 cathode is fed from the M1S rail through a 1k resistor R7 which establishes the recommended minimum operating current for the TL431 of 1mA down to a voltage on the M1S net of just over 3.5V even with the additional load of the two 100k resistors to ground, R14 and R16.
The 1nF capacitor, C6 provides frequency compensation for stable operation of U1 as described in the literature for the TL431.
To understand how this section works, assume for the moment that:
i) Q1, the open collector pullup transistor, is not fitted;
ii) Q3, the right hand side of the long tailed pair, is not fitted;
iii) Q7, the Timeout interval reset transistor is not fitted.
The core of the overvoltage protection circuit comprises half of the LMC6482 rail-to-rail-input-and-output opamp, U2.1, pullup OR-ing diode D3, P channel MOSFET, M2, gate pulldown resistor, R18, voltage setting resistors, R6 and R11 and frequency compensation components R8 and C4.
When the voltage on the FB1 net is below 2.5V, i.e. the voltage on the M1S net is below
2.5*(1+R6/R11) = approximately 6V, then the output of U2.1 falls to within a few mV of ground.
The output of U2.1 drives the gate of M2 through D3
The gate of M2 is pulled to ground through R18 so there is no current flow through D3. Hence M2 is turned fully on. This connects the M1S net through the 10mR current sense resistor R5 and the net M2S to the load net through a low resistance path.
Even with a load current of 1A or so, the voltage on the FB1 net will then be only a few tens of mV below the input supply voltage..
During an input overvoltage event the input supply voltage rises so the voltage on the load net rises. When this voltage exceeds:
2.5*(1+R6/R11) = 5.96V
the voltage on the FB1 net will exceed 2.5V. This will make the output of U2.1 rapidly rise towards the voltage on the M1S net. This will cause the gate voltage of M2 to be pulled up to one diode drop below the output voltage of U2.1.
Reducing the gate source voltage of M2 in this way will start to turn it off. As it turns off, M2 drain source resistance rises and so develops a significant voltage drop across it due to the load current flowing through it. Therefore the voltage on the load net can no longer increase with the input supply voltage.
The negative feedback loop from the (inverting) drain output of M2 to the (non-inverting) input of U2.1 causes the circuit to linearly regulate the output voltage on the load net to 5.96V.
Because M2 represents some additional voltage gain and phase shift around this negative feedback loop, external frequency compensation is required for stable operation, i.e. to stop the circuit oscillating, when in regulation. This is provided by R8 and C4.
If the Timeout interval comparator.is disabled due to the omission of Q3, the overvoltage circuit stays in regulation until the input supply voltage dropped below 5.96V again and the circuit would revert to being a simple low resistance path.
To understand how this section works, assume now that the open collector pullup transistor, Q1 is fitted but that Q3 and Q7 are not fitted.
The voltage at the base of PNP buffer transistor, Q4, from the REF1V25 net is 1.25V therefore the voltage at the emitter Q4 is one base emitter drop above 1.25V.
The voltage at the emitter of Q2, the left hand side of the long tailed pair is at one diode drop below the emitter of Q4, i.e. it is at approximately 1.25V.
To a first approximation, this arrangement cancels out the two base emitter drops and their associated 2mV/degC temperature drifts to provide an accurate and temperature stable 1.25V at the emitter of Q2
Therefore the emitter current of Q2 is set by the voltage across R17, i.e.
1.25V/R17. Since the base current of Q2 is only about 1/200 of the emitter current and so can be considered negligible, the collector of Q2 forms a constant current sink with a current defined by
1.25/R17. This sets the collector current of Q2 at 125uA.
This current is pulled from the M1S net through the current limit setting resistor R1. The voltage on the IREF net at the inverting input of U2.2 is therefore
125uA*R1 = 25mV below the voltage on the M1S net.
With a load current of 1A, the voltage drop across the current sense resistor, R5, is 10mV therefore the voltage at the non-inverting input of U2.2 is 15mV above the voltage on the M1S net. The gain of U2.2 means that the voltage on the IOPOUT net is pulled up to within a few mV of the voltage on the M1S net. This holds the base of the open collector pullup transistor, Q1 at almost exactly the same voltage as the emitter so Q1 is off.
As the load current increases then so does the drop across R5. As soon as this drop exceeds 25mV, i.e. at a load current of 2.5A, the non-inverting input of U2.2 will drop below the inverting input. The gain of U2.2 will switch the voltage on the IOPOUT net towards ground, turning Q1 on.
As Q1 turns on, it starts to source current into the gate pulldown resistor R18, pulling the gate of M2 up towards the voltage M1S net. In other words, M2 starts to turn off. This makes the drain to source resistance of M2 rise and so the voltage drop across it increases causing the voltage on the LOAD net to fall and so opposing the increase in load current.
Thus, the negative feedback around U2.2, Q1 and M2 works to maintain a constant current limit of 2.5A to the load.
The additional voltage gain and phase inversion of Q1 and the phase shifts of Q1 and M2 mean that some external frequency compensation is required to maintain the stability of this feedback loop when operating in constant current limiting mode. This is provided by R4 and C3. Stability is also assisted by the fast turn-on/slow turn-off of Q1 via the parallel diode and resistor combination of D1 and R2.
The function of D1 and R2 will be explained when describing the Timeout interval and comparator with switched current sink outputs.
As the output voltage falls in response to the current limiting action, if the voltage on the VFB net drops below 2.5V, the voltage regulation circuit based on of U2.1, D3 and M2 will try to turn M2 harder on to maintain the output voltage at the required level. To avoid this contention, the output of U2.1 is connected through the diode D3 so that as Q1 pulls the gate of M2 up, if U2.1 tries to pull the gate down, D3 becomes reverse biased and disconnects the output of U2.1 so it has no effect.
In this way the current limit circuit has precedence over the voltage regulation in the control of M2. However, this does not stop the overvoltage clamping action from operating if required even if the circuit is in current limit because overvoltage clamping also tries to turn M2 off by driving the gate more positive. Therefore, if the overvoltage clamping action requires M2 be turned harder off than the demand from the current limit circuit, it will try to drive the gate more positive that the current from Q1 is pulling it and so D3 will conduct and - because it is driven by the ow impedance voltage source output of U2.1, the gate of M2 will be pulled up, overriding the pullup demand of Q1.
It can be seen therefore that in effect, D3 forms an analogue wire-OR function with the collector of Q1.
To understand how this section works, assume now that the open collector pullup transistor, Q1 is fitted and that the right hand side of the long tailed pair,Q3, is also fitted but Q7, the Timeout interval reset transistor, is not fitted.
The voltage on the gate of M2 (the GATE net) is buffered by the emitter follower, Q5, so the voltage on the TIMEOUT net is equal to that on the GATE net plus the base emitter drop of Q5.
The emitter of Q5 is pulled up by a 1M resistor. There is also a 100nF capacitor, C7, connected between the TIMEOUT net to ground. The emitter of Q5 can pull down relatively hard but it can only be pulled up through R13 so as the voltage on the TIMEOUT net can fall rapidly but rise only with an RC time constant of
1M * 100n = 100ms.
The voltage on the TIMOUT net is fed to the base of Q3 which together with Q2 is connected as a long tailed pair. This forms a simple comparator where the base of Q3 is fed via the base emitter voltage cancelling buffer Q4, by a 1.25V reference voltage and the base of Q3 is fed via the base emitter voltage cancelling buffer Q5 and the RC charging circuit of R13 and C7, by the voltage on the GATE net.
The combination of the base emitter voltage cancelling buffers and the long tailed pair means that the comparator is fed by accurately defined voltages with temperature stable switching thresholds and performance.
As described in the section on current limiting protection, the voltage at the emitter of Q2 is set to 1.25V. Therefore, the emitter of Q3 is also pulled up to 1.25V. Hence, when the voltage on the TIMEOUT net is below 1.25V, the base emitter junction of Q3 is reverse biased so Q3 is off and generates zero collector current (neglecting a very small leakage current). Hence - neglecting the small base current of Q2 - the full current of 125uA passing through R17 is sunk through the collector of Q2 to define the current limit threshold voltage across R1.
If the gate of M2 is pulled up towards the voltage on the M1S net - either by the operation of the overvoltage clamp or the current limiting protection circuits - the voltage on the TIMEOUT net climbs more slowly due to the time constant formed by R13 and C7.
If the gate of M2 then drops back towards ground, because the overvoltage or overcurrent event had passed then the voltage on the TIMEOUT net is pulled rapidly down by the low source resistance presented by the source follower action of Q5.
Once the voltage on the TIMEOUT net rises above the voltage at Q4 emitter, i.e. 1.25V plus one base emitter drop, the base emitter junction of Q3 starts to be forward biased so Q3 begins to turn on. As it does so, it starts to lift the voltage at the emitter above the 1.25V set by Q2 and so starts to reduce the forward bias of the base emitter junction of Q2 beginning to turn it off. It is shown in the Long tail pair 2 simulation in the following project:
that increasing the voltage at the base of Q3 by about 300mV with respect to the base of Q2 is enough to steer the tail current through R17 from 90% flowing through Q2 and 10% flowing through Q3 to 10% through Q2 and 90% through Q3.
Thus if the base of Q3 is pulled up by the voltage on the TIMEOUT net being driven up by a rising voltage on the GATE net, the current through Q3 starts to increase rapidly from zero to at least the full 125uA through R17 (although in fact it will increase somewhat as the emitter of Q3 is pulled up by the voltage on the TIMOUT net) by a relatively small change in the voltage on the TIMEOUT net.
As the current out of the collector of Q3 rises it pulls current through the base of Q1, turning it on.
If Q1 is off because there is no over current event present causing it to be turned on, the output of U2.2 will be very close to the voltage on the M1S net so D3 will be reverse biased as the base of Q1 is pulled below this voltage by the collector current of Q3. This turns Q1 on and - with the the current gain in Q1 - pulls the voltage on the GATE net hard up to that on the M1S net, turning M2 off.
This disconnects the load from the input supply.
Even if Q1 is already being turned on by the output of U2.2 in response to an overcurrent event, the presence of D1 ensures that almost all the collector current of Q3 is drawn through the base of Q1. The additional current into the base of Q1 turns it on more than the output of U2.2 may be already and so pulls the voltage on the GATE net even higher so turning M2 off as described above.
If the voltage on the GATE net is already being raised by the output of U2.1 in response to an overvoltage event, the presence of D3 ensures that as the collector current of Q1 pulls the voltage on the GATE net up, D3 is reverse biased and so once again, M2 is turned fully off.
Because the voltage on the TIMEOUT net is effectively just a low pass filtered version of that on the GATE net (and the base emitter voltage offsets of Q4 and Q5 are cancelled out by the emitter follower buffers) essentially as soon as the voltage on the GATE net rises to just below about 1.25V the increasing collector current of Q3 turns Q1 on which pulls the GATE net up which increases the collector current of Q3. This creates a positive feedback loop which means that as the voltage on the GATE net rises to near 1.25V, the comparator works to very rapidly pull the GATE voltage up to the voltage on the M1S net. This switches M2 very quickly and - because the voltage on the GATE net is held up by Q1, holds M2 off.
The only way to to break this latching off action of M2 is to remove the input power to the whole circuit and then reapply it or to briefly pull the voltage on the TIMEOUT to ground, discharging C7 at the same time. Once this discharge path is removed then whatever protection circuit that may be active then pulls the GATE net back up and the TIMEOUT period starts again. If there is no protection circuit active at the time that the discharge path is removed then the circuit will resume normal operation with M2 fully on.
As discussed above, although possible, it is not advisable to to perform this reset action of discharging of C7 manually via a simple pushbutton switch because the time taken to do this may be longer than the TIMEOUT period which is set to protect M2 from overheating in overvoltage and/or overcurrent protection conditions.
The preferred solution is to do this reset action using an automatic timer circuit.
This is described in the next section.
The overvoltage and current limit protection circuit offers functionality similar to that of the LT4356-3 Surge Stopper with Fault Latchoff from Linear Technology.
To understand how this section works, assume now that Q1, the open collector pullup transistor, Q3, the right hand side of the long tailed pair and Q7, the Timeout interval reset transistor are all fitted.
D5 and R24 produce a voltage on the GATEREF net of one diode drop, i.e. approximately 0.6V, below the voltage on the M1S net.
This voltage is fed to the inverting input of the one half of the LMC6482 dual rail to rail input and output opamp, U3. The non-inverting input of U3.1 is fed by the voltage on the GATE net. U3.1 operates as a comparator with the output driving the FAULT indication LED via current limiting resistor R19 and PNP Reset Timer Enable transistor Q6, via R23.
The other half of the dual opamp, U3.2 together with R20, R21, R22, R26, R27, D7 and C9 forms a relaxation oscillator.
In normal operation, i.e. no overvoltage or overcurrent protection in process, the voltage on the GATE net is very close to ground which is well below the voltage on the GATEREF net so the output of U3.1 is pulled low. This turns D6 off and Q6 on.
When Q6 is on, the voltage on C9 is rapidly charged up and held to within about 200mV (i.e. the Vce_sat of Q6) of that on the M1S net. This causes the output of U3.2 to drop to within a few mV of ground and so hold the Timeout Interval Reset transistor, Q7, off and reverse biasing D7.
This also pulls the voltage on the HYST net down to:
VHYSTLO = V(M1S)*(1M//100k)/(1M+1M//100k)
VHYSTLO is the voltage on the HYST net when the output of U3.2 is low;
V(M1S) is the voltage on the M1S net;
1M in parallel with 100k.
An overvoltage or overcurrent fault that exists for longer than the TIMEOUT interval will cause Q1 to turn on, latching M2 OFF by pulling the voltage on the GATE net up to within about 200mV (i.e. the Vce_sat of Q1) of that on the M1S net.
This voltage on the GATE net is above the voltage on the GATEREF net so U3.1 pulls the voltage on the FAULT net up to within a few mV of that of the M1S net turning the fault indication LED on and Q6 off.
As soon as Q6 turns off, the voltage on C9 decays exponentially towards ground as C9 is discharged - by the low output voltage of U3.2 - through R20. When the voltage across C9 drops below VHYSTLO, the output of U3.2 rises to within a few mV of the voltage on the V(M1S) net, forward biasing D7 and turning on the Timeout Interval Reset transistor, Q7.
Neglecting the forward drop of D7, forward biasing it effectively throws R27 in parallel with R20 so beginning to charge C9 back up towards the voltage on the M1S net approximately 10 times faster than R20 discharged it towards ground.
At the same time however, turning on the Timeout Interval Reset transistor, Q7, also rapidly discharges the voltage on C7 to ground. This turns Q3 off and so Q2 on. This steers the tail current of the long tailed pair from through Q3 to through Q2 and hence through the current limit setting resistor R1. This returns the control of Q1 back to the current limit circuit and therefore the control of the voltage on the GATE net back to the current limit and overvoltage protection circuits.
If there is an overvoltage or overcurrent event present at this point, then when Q1 turns off, the voltage on the GATE net will fall but will remain at somewhere between about 1.5V and about 2.5V below the voltage on the M1S net. This is below the voltage on the GATEREF net so the output of U3.1 switches low, turning Q6 on. This rapidly pulls the voltage on the RC net back up to that on the M1S net so the output of U3.2 switches low, reverse biasing D7 and turning Q7 off, allowing the voltage on the TIMEOUT net to rise again, eventually turning Q3 and Q1 on again, pulling the voltage on the GATE net back up to that on the M1S net and so (a) latching M2 off and (b) starting the automatic reset timing process again.
If there is no overvoltage or overcurrent event present at the point where Q7 turns on, then when Q1 turns off, the voltage on the GATE net will fall to ground. This is below the voltage on the GATEREF net so the output of U3.1 switches low, turning Q6 on. This rapidly pulls the voltage on the RC net back up to that on the M1S net so the output of U3.2 switches low and turns Q7 off. Under these conditions the TIMEOUT net climbs back to only one diode drop above ground so Q3 is held off, M2 is held fully on and the voltage on the GATE net remains under the control of the overvoltage and current limit circuits. Q6 remains on so the reset timer is disabled.
After the output of U3.2 goes high and Q7 turns on, if for any reason the voltage on the GATE net stays above that on the GATEREF net then Q6 will be held off by the output of U3.1 and, neglecting the forward drop in D7, the high output U3.2 will cause the voltage on the RC to ramp up effectively through R20//R27 through until it crosses a threshold voltage of:
VHYSTHI = V(M1S)*(1-(1M//100k)/(1M+1M//100k))
VHYSTHI is the voltage on the HYST net when the output of U3.2 is high;
V(M1S) is the voltage on the M1S net;
1M in parallel with 100k.
The output of U3.2 will then go low, turning Q7 off and starting the reset timing cycle again.
This prevents Q7 getting stuck on and permanently disabling the TIMEOUT function.
Under these conditions and with the component values shown, the time to charge C9 through R20//R27 (3ms) is approximately 1000 times shorter than the discharge time through R20 alone (3s) and about 10 times longer than the time taken to charge C9 through Q6 (300us).
These charging times for C9 mean that if there is an overvoltage or overcurrent event, then even if for some reason the voltage on the GATE net is not pulled below the voltage on GATEREF as a result of a high output on U3.2 causing the C9 to be discharged and so resetting the output of U3.2 low about 300us later, then the output of U3.2 will automatically go low after about 3ms simply as part of the relaxation oscillator timing. This 3ms is considerably longer than the normal 300us reset time and so has no effect on normal reset timings shorter and is also considerably shorter than the TIMEOUT interval and so has negligible effect on the reset TIMEOUT and reset timings compared to a normal reset operation.
The TIMEOUT interval is roughly 15ms which is long enough for a single overvoltage event, of a duration around that of half a mains cycle, to be clamped without the TIMEOUT expiring. Repeated input overvoltage (or output overcurrent) events will still cause the voltage across C7 to ramp up but towards a final voltage determined by the input overvoltage and the duty cycle between the normal and the overvoltage event timings. This means that for frequent repetitive overvoltages, although the voltage on C7 climbs more slowly than for a continuous overvoltage or overcurrent event, it will still exceed the level at which Q3 turns on and - bearing in mind that the average dissipation in M2 is reduced due to the duty cycle of the overvoltage or current events - so still latches off M2 before it overheats.
The operation of the TIMEOUT and reset timings means that the green LOAD LED turns OFF after the first TIMEOUT interval of about 15ms for a continuous overvoltage or overcurrent event (except for a dead short across the output whereupon the LOAD LED obviously goes OFF immediately) and flashes ON for about 15ms approximately every 3s, until the overvoltage or overcurrent event ceases or input power is removed.
Note that the FAULT LED may appear to turn off slowly due to the total decoupling capacitance across the protected output supply rail.
At the same time, the FAULT LED will turn ON after the first TIMEOUT interval of about 15ms for a continuous overvoltage or overcurrent event and flashes OFF for about 15ms approximately every 3s, until the overvoltage or overcurrent event ceases or input power is removed. Note that if the reset timer cannot cause the voltage on the GATE net to be pulled below the voltage on the GATEREF net then the FAULT LED will not flash OFF but will illuminate steadily until the overvoltage or overcurrent event ceases or input power is removed.
Uberclamp fault latching simulation schematicOpen in editor
Uberclamp with auto retry and reverse polarity protection simulation schematicOpen in editor
auto_retry_timerOpen in editor
Uberclamp with auto retry and reverse polarity protection simulation schematic DMP4015SK3Open in editor
Uberclamp final circuitOpen in editor