DR658

Custom DIY W65C02/W65C816 SBC with configurable (trough CPLD) interconnection logic. (1st prototype; not tested)

Nearly all logic is located inside CPLD (either MAX II 240 or 570)

Target CPU clock 6.25 MHz. Max CPU clock is 8MHz (speed limit for 3V3).

RAM is choosen accordingly (55ns 3v3 and cheap)

ROM is of SPI type (3v3 and cheap). Interface transition to/from parallel is handled by CPLD.

SPI access has a performance penalty. Transparent implementation needs to hold CPU until transfer is complete.
It can be accessed as a regular ROM at specific addresses as like generic SPI device.
There should be no SPI device access active when accessing SPI ROM. Otherwise SPI device command sequence will be corrupted by SPI ROM access sequence!!
For 25MHz main oscillator:
SPI ROM takes 11 CPU cycles to read memory location (full address is silently transferred each time)
SPI port takes 3 CPU cycles to either read or write byte.

UART connectors have additional pin used (pin 10) for 3v3 power delivery. This is to simplify external interface/level adapter connection (can be powered from board).

VGA is an optional feature (main connection is expected to go trough UART). Simple VGA should be possible even with EPM240 (maybe with some Atari 2600 style restrictions/simplifications)

Joystick port basically represents 6 custom connection lines. The intent is to make NES/SNES compatible port but not limited to.

System interface exposes 8-bit data, 16-bit address (instead of full 24-bit) and 8 custom user control/status lines (so different standards can be implemented using CPLD)