**CAUTION! UNTESTED – WORK IN PROGRESS – UNDER CONSTRUCTION** Added to jlcpcb order ``` Specs One 512K EEPROM or RAM or NVRAM One to Four 30 PIN or One 72 PIN DRAM SIMM EPM7128 84pin PLCC - DRAM Controller & Memory Mapper Linear or Paged operation – RomWBW compatible DRAM CARD - On Card Refresh, looks like SRAM to CPU - Memory retained during CPU Single-Step or HALT - Up to 16MB Linear for z280 / others - Wait States can be added for slow EEPROM or DRAM Options – if it is possible... - Load a test ROM file via Intel Hex into DRAM and map it low for fast testing... - Load a test ROM file and write it to the EEPROM. - "SHADOW" the EEPROM to eliminate wait states. Future – if it is possible... - "Software Select" Linear or Paged memory mapping on the fly. - 32MB or 64MB DRAM paged as 256×128k or 256k pages ```