Editor Version ×
recommended

Pro Edition

free

Brand new interactions and interfaces

Smooth support for design sizes of over 3W

devices or 10W pads

More rigorous design constraints, more

standardized processes

For enterprises, more professional users

Std Edition

Easy to use and quick to get started

The process supports design scales of 300

devices or 1000 pads

Supports simple circuit simulation

For students, teachers, creators

Ongoing

STD Spartan 6 FPGA Board

Spartan 6 FPGA Board

Project tags

License

CC-BY-SA 3.0

License: CC-BY-SA 3.0

Mode:

Mode

Editors' pick

Editors' pick

  • 5k
  • 0
  • 6
Update time: 2023-04-17 01:46:32
Creation time: 2019-01-05 09:19:58
Description

Description

Edit Oct 11th, 2021: This was meant as a personal project but I decided to make it public. This is the first large PCB I've made and so there are probably some design flaws that a professional designer wouldn't make, so feel free to drop some comments so we can both learn together. I've finally gotten it to work after 2 ish years from when the idea started and it works great. I was so so happy and excited when I got a blinking program to work. So far I've even been able to make it render the Mandelbrot set and send it over vga to my monitor. I haven't worked on this project in a while but I thought I should add this edit so that my project would be of more use to people. Maybe I'll revisit this someday and improve my design, make more stuff, and share some code. Tips and To-do's: * The first design had a flaw where I forgot to route the crystal clock pin to the fpga chip, I've updated the current design but all my boards now have a tiny piece of wire that connects the clock to an underside clk pin on the bga. * I've learned that the secret of soldering bga chips is using a good quality solder paste, don't use expired bismuth based paste like I did before, invest in a good quality lead based solder, It will make the process more enjoyable too. * Looking back, the way I routed my power and ground traces is not something I'm super proud of. track lengths can be minimized, and bypass capacitors can have less line inductance to the fpga chip, further more I'd like to add a ground plane, as good practice for minimizing electromagnetic interference. * Adding more I/O for pins other than the fpga's IO_LXXY_# pins would be smart so you could do stuff like properly route clocking stuff in and out of the fpga though a male header pin. This is something I didn't know about before taking on this project, maybe I'll make videos to share what I've learned so people can learn about fpga's and how to program them. Fig 1: The Mandelbrot set generated by the fpga and sent over VGA to a computer monitor. ![mandelbrot small.jpg](//image.easyeda.com/pullimage/7DLIkxPymMBmajmOhhB55dH8iD2LCR3leOYcRoQj.jpeg) Fig 2: Completed functional board, running a blinking program. ![board small.jpg](//image.easyeda.com/pullimage/1UATAZIPOuEmVZJe1icTigofmyo6Ehf569Td9gy4.jpeg) Fig 3: While implementing a three color greyscale checkerboard to display over NTSC to a rear view car monitor, an unintentional bug related to using bit shifting instead of addition caused this unexpected pattern to be displayed. ![idk small.jpg](//image.easyeda.com/pullimage/nIZHBqeOTVpiL28qGD1P9dSquSCdSOo1FyTmLPx4.jpeg)
Design Drawing

Design Drawing

schematic diagram
1 /
PCB
1 /
The preview image was not generated, please save it again in the editor.
ID Name Designator Footprint Quantity
1 FP6165ADXR-G1 U3 SOP-8_EP_150MIL 1
2 50MHz X1 SMD-7050_4P 1
3 AZ1117EH-3.3TRG1 U1 SOT-223 1
4 Header-Male-2.54_1x6 P1 HDR-6X1/2.54 1
5 4.7uH L1 SMD-8.0X8.0-2P-0840 1
6 100nf C13,C4,C6,C7,C11,C12 0402 6
7 micro USBFemale USB1 MICRO-USB-1 1
8 PTS635SH43SMTRLFS SW1,SW2,SW3 KEY-6.0X3.5X4.3MM 3
9 15pf C3,C8 0402 2
10 1u C5,C10 0603 2
11 4.7k R13,R14,R15,R16,R17,R18,R3 0402 7
12 330uF C1 CAP-D6.3XH7.7 1
13 100uF C2,C9 CAP-T-5*5.4 2
14 W25Q16JVSSIQ U4 SOIC-8_208MIL 1
15 Header IO 1 H2 210S-1X8P 1
16 Header IO 2 H3 210S-1X8P 1
17 LED-Red(0805) LED2,LED1,LED3,LED4,LED5,LED6 LED-0805 6
18 5v Header H1 HDR-2X1/2.54 1
19 1k R8,R9,R10,R11,R12,R7,R6,R4,R5 0805 9
20 200k R1,R2 0805 2
21 XC6SLX16-2FTG256C U2 FBGA-256 1

Unfold

Project Attachments

Project Attachments

Empty
Project Members

Project Members

Target complaint
Related Projects
Change a batch
Loading...

Comment

Add to album ×

Loading...

reminder ×

Do you need to add this project to the album?

服务时间

周一至周五 9:00~18:00
  • 0755 - 2382 4495
  • 153 6159 2675

服务时间

周一至周五 9:00~18:00
  • 立创EDA微信号

    easyeda

  • QQ交流群

    664186054

  • 立创EDA公众号

    lceda-cn