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2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

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1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

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STD 20 WATT CLASS A

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Update time: 2019-11-07 23:47:39
Creation time: 2018-04-16 23:07:38
Description
Test
Design Drawing
schematic diagram
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PCB
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ID Name Designator Footprint Quantity
1 BD139 Q2,Q6,Q9 BD139 TO-126 3
2 1u C1 RAD-0.1 1
3 22K R2 RES 1
4 100k R3 RES-ADJ_3386P 1
5 22OR R4 RES 1
6 BC559 Q3,Q1 TO-92(TO-92-3)_1 2
7 22k R5 RES 1
8 1k R6 RES 1
9 22u C2 RAD-0.1 1
10 1k5 R7,R8 RES 2
11 2K2 R1,R13 RES 2
12 100p C3 RAD-0.1 1
13 6K8 R9 RES 1
14 2Pin Header H1 2PIN HEADER 1
15 100u C4 CAP-D3.0XF1.5(LEO) 1
16 220R R10,R17 RES 2
17 0R25 R18 RES 1
18 BC549 Q10 TO-92(TO-92-3)_1 1

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