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STD Rising-edge trigger R-S Flip Flop circuit
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License: GPL 3.0
Description
The normal R-S flip-flop circuit includes two nade gate are connected together and when need to set or reset then feed the logic signal is “1” instead of trigger and use inverter work instead. Read more : [**Rising-edge trigger R-S Flip Flop circuit**](https://www.eleccircuit.com/Rising-edge-trigger-R-S-Flip-Flop-circuit/)
Design Drawing
schematic diagram
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PCB
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | 4069 | N1,N2 | NONE | 2 |
| 2 | 1N4148 | D1,D2 | DO-35 | 2 |
| 3 | 4.7M | R1,R2 | AXIAL-0.3 | 2 |
| 4 | 180K | R3,R4 | AXIAL-0.3 | 2 |
| 5 | Header-Male-2.54_1x1 | Q,R,S | HDR-1X1/2.54 | 3 |
| 6 | Q | _ | HDR-1X1/2.54 | 1 |
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