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STD V2164 VCA simulation demo

License: Public Domain

Mode: Editors' pick

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Update time: 2020-12-22 22:53:42
Creation time: 2020-10-15 21:43:09
Description
Demonstrating one channel of the V2164 quad VCA using a spice model developed for EasyEDA by signality.co.uk *** AFTER PLACING V2164D.5: CHANGE NAME TO V2164_bias *** Simulatable Spice Symbols for the V2164 VCA * Models developed by signality.co.uk. 200521 ** * This is a purely behavioural model and its use is subject to the following limitations. * The quoted gain constant and temperature coefficient are accurately modelled. * Exponential Control Voltage Law: The adherence of the gain vs. control voltage to an exponential law may be slightly more accurate at the extremes of control range compared to the real device. * Frequency Response and Instability: There is insufficient information in the datasheets for any of the various versions of the 2164 type VGA - original SSM or Analog Devices versions of the SSM2164, the CoolAudio V2164 or the re-engineered SSI2164 from Sound Semiconductor - from which to accurately model the frequency response vs. gain and therefore to model the exact behaviour of the instability which the input RC compensation network is required to stabilise. * This model has a best guess attempt at modelling a frequency response which results in instability at gains of 0dB and which the recommended input RC compensation network does indeed stabilise. * THD and Noise: Not currently modelled. * Input bias and output offset currents: Not currently modelled. * Control voltage feedthrough: Not currently modelled. * Power Supply Rejection Ratio (PSRR): Not currently modelled. * How to use the models: The V2164_amp blocks simulate and can be used separately. To model the power supply drain of a complete V2164 device including the MODE current, the V2164_bias block must be placed in the simulation. *** Note however that the MODE current fed into the V2164_bias block has no effect on the THD or the noise performance of the V2164_amp model. ***
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ID Name Designator Footprint Quantity
1 15 VNEG2,VPOS2 2P-5.0 2
2 sin(0 {0.775*sqrt(2)} 2k) AC 1 0 VIN4 2P-5.0 1
3 510R R3 R_AXIAL-0.3 1
4 560p C1 C_MLCC_RES_DIP_5.5X3MM_P5MM 1
5 30k R9,R11 R_AXIAL-0.3 2
6 220p C3 C_MLCC_RES_DIP_5.5X3MM_P5MM 1
7 47n C6,C7 C_MLCC_RES_DIP_5.5X3MM_P5MM 2
8 7.5k R18 R_AXIAL-0.3 1
9 PULSE(3.3 -0.65 0 10m 10m 0 1) V1 HDR1X2 1
10 V2164_amp U3 V2164D 1
11 TL071EE U4 ? 1

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