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2.The process supports design scales of 300 devices or 1000 pads

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STD PODEANU ALEXANDRU - 8414 -PROIECT EA - SCHEMA SURSA 2

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License: Public Domain

Creation time: 2019-01-06 21:06:28
Update time: 2019-01-06 21:06:31
Description
Design Drawing
schematic diagram
1 /
PCB
1 /
Empty
ID Name Designator Footprint Quantity Mounted
1 TPS54232DR U1 SOIC-8_150MIL 1 Yes
2 10uF CIN CAP-CBB-6.5*4.0 1 Yes
3 24.4 kOhm RENB RESISTOR 1 Yes
4 Resitor2 RENT RESISTOR 1 Yes
5 44.2 kOhm RCOMP RESISTOR 1 Yes
6 8.2nF CSS CAP-CBB-6.5*4.0 1 Yes
7 820pF CCOMP CAP-CBB-6.5*4.0 1 Yes
8 15pF CCOMP1 CAP-CBB-6.5*4.0 1 Yes
9 100nF CBOOT CAP-CBB-6.5*4.0 1 Yes
10 5KP36A_C303791 D1 DIODE_P600_HORIZONTAL 1 Yes
11 15uH L1 L-10UH 1 Yes
12 10.2 kOhm RFBT RESISTOR 1 Yes
13 1.02 kOhm RFBB RESISTOR 1 Yes
14 10uF COUT CAP-CBB-6.5*4.0 1 Yes
15 SIN(0 1 50) IOUT 2P-5.08 1 Yes
16 DC 9V VIN HDR1X2 1 Yes

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