OngoingProjeto 5
STDProjeto 5
116
0
0
0
Mode:Full
License
：Creation time:2022-03-08 14:23:35Update time:2022-03-15 14:38:22
Description
PORTA LOGICAS BÁSICAS COM TRANSISTORES
Design Drawing
The preview image was not generated, please save it again in the editor.BOM
Bom empty
CloneAdd to Album
0
0
Share
Report
Project Members
Followers0|Likes0
Related projects
Empty
Comment