Log Peak Detector - Simulation - EasyEDA open source hardware lab

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STD Log Peak Detector - Simulation

License: CC-BY-SA 3.0

Mode: Editors' pick

Update time： 2021-12-04 12:33:47

Creation time： 2020-02-11 10:44:55

Description

Simulation setup for a fast log pulse peak detector designed to be used in conjunction with the MuonPi HAT.

Design Drawing

schematic diagram

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PCB

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BOM

ID	Name	Designator	Footprint	Quantity
1	1p	C8,C5,C11	RAD-0.1	3
2	5	V3	HDR1X2	1
3	0.01	R5,R117	AXIAL-0.3	2
4	10	R1,R23,R15	AXIAL-0.3	3
5	10k	R3	0805	1
6	100n	C3	0805	1
7	0.001	R116	AXIAL-0.3	1
8	1Meg	R100	AXIAL-0.3	1
9	0.005	V102	HDR1X2	1
10	TLV3501	U102	SO-8	1
11	0.1p	C103	0805	1
12	Dmmbd770t1g	D100,D101,D102,D3,D4,D5,D2	SMC	7
13	470k	R2,R26,R30	AXIAL-0.3	3
14	10n	C1	0805	1
15	1n	C4	0805	1
16	100k	R6,R22	AXIAL-0.3	2
17	10Meg	R8	AXIAL-0.3	1
18	100	R11,R12,R28	AXIAL-0.3	3
19	22p	C6	0805	1
20	10p	C10	0805	1
21	99.9k	R20,R24	AXIAL-0.3	2
22	1p	C19	0805	1
23	100Meg	R25	AXIAL-0.3	1
24	Ammeter	A1	NONE	1
25	4.7k	R108	0805	1
26	1k	R110	0805	1
27	10n	C106	RAD-0.1	1
28	1	R111	0805	1
29	BSS98	Q100	TO-92(TO-92-3)	1
30	220	R112	0805	1
31	100k	R113,R10	0805	2
32	0.1p	C107,C2	RAD-0.1	2
33	10	R118	0805	1
34	50G	R121,R123	0805	2
35	300G	R103	0805	1
36	470k	R208	0805	1
37	10k	R9	AXIAL-0.3	1
38	2.2k	R27,R4,R17,R16	AXIAL-0.3	4
39	V=(1e-1white(5e6time))	B2	NONE	1
40	1N4148	D1	DO-35	1
41	PWL(150u 0 +10u 0 +1n -0.2 +5n 0.04 +20n 0 +30u 0 +1n -0.1 +5n 0.02 +20n 0 +30u 0 +1n -0.3 +5n 0.06 +20n 0 +30u 0 +1n -0.1 +5n 0.02 +20n 0 +50u 0 +1n -0.1 +5n 0.02 +20n 0 +50u 0 +1n -0.2 +5n 0.04 +20n 0 +50u 0 +1n -0.3 +5n 0.06 +20n 0 +50u 0 +1n -0.5 +5n 0.1 +20n 0) AC 1 0	V1	HDR1X2	1
42	100p	C7	RAD-0.1	1
43	470n	C16	RAD-0.1	1
44	220p	C15,C12	RAD-0.1	2
45	2p	C14,C13	RAD-0.1	2
46	22p	C22	RAD-0.1	1
47	0.5p	C21	RAD-0.1	1
48	Multimeter	XMM1,XMM2		2
49	1u	L1	AXIAL-0.4	1
50	27n	L2	AXIAL-0.4	1
51	OPAMP5PEE	U4,U3,U5,U8	DIP08	4
52	DFFEE	U7	NONE	1
53	1k	R19	AXIAL-0.3	1
54	1.025k	R18	AXIAL-0.3	1
55	51	R14	AXIAL-0.3	1
56	100K	R13,R7	AXIAL-0.3	2
57	ADA4940	U1	NONE	1

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