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STD MuonPi Analog Pulse Processor Plug-On Board V2

License: CC-BY-SA 3.0

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Creation time: 2020-07-26 18:11:12
Update time: 2021-12-04 12:32:52
A peak detector (PD) for measuring the amplitude of ultra-fast (few ns) pulses originating e.g. from SiPM or PMT photo detectors used in nuclear and particle physics. The PCB is designed as plug-on board for the [MuonPi base PCB](https://easyeda.com/hgzaunick/cosmic_shower_detector_v1-52b8a2536bb6468e9f48412a774951d0_copy_copy) (version 3.0 or higher). The PCB is laid out as 2-layer board for rapid prototyping. The amplification has two different gains (low/high gain selection from base PCB). The input to the first sample-hold (SH) stage is decoupled and dumped through a forward-biased Schottky barrier diode (MMBD770 or similar; the important parameter here is a very low minority-carrier lifetime yielding ultra-fast switch on/off times) onto an integration capacitor. The capacitor's voltage is buffered by an opamp with low input bias current, amplified and low-pass filtered. The selected opamp is an inexpensive GBP=100 MHz quad opamp TLV3544 (TI). This stage translates the short ns pulse into pulses with decay time in the us range without decreasing the amplitude by the same amount, as would be the case for a simple low-pass filter. The second part, which is the actual peak detector (PD) utilizes the remaining three opamps to drive the storage capacitor through a network of fast Schottky diodes and to isolate this capacitor with its ultra-high input impedance to avoid droop (drain of the capacitor charge due to leakage). Furthermore, two n-MOSFETs offer a fast reset of the storage cap (t_r>=100ns). Droop is further reduced by bootstrapping the potentials at the pins of the second series diode and drain and source potential of the high-side MOSFET of the reset switch circuitry and thus nulling leakage through these components. With this last stage the pulse amplitude is clamped and held indefinetely to provide a sampling/digitization at low rates and speed until a reset pulse is applied.
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schematic diagram
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ID Name Designator Footprint Quantity
1 10n C1 0805 1
2 TP3 P3 HDR-1X1/2.54 1
3 TP2 P2 HDR-1X1/2.54 1
4 TP1 P1 HDR-1X1/2.54 1
5 TP5 P5 HDR-1X1/2.54 1
6 22p C26 0805 1
7 BSS123 Q3,Q2 SOT-23(SOT-23-3) 2
8 BAT54 KL1 D2 SOT-23(SOT-23-3) 1
9 BAT54SLT1 D3 SOT23-3 1
10 120 R28 0805 1
11 10k R27,R26,R25,R31,R10,R3,R12 0805 7
12 22 R30 0805 1
13 2N7002 Q1 SOT-23(SOT-23-3) 1
14 TP4 P4 HDR-1X1/2.54 1
15 TP7 P7 HDR-1X1/2.54 1
16 TP6 P6 HDR-1X1/2.54 1
17 TP8 P8 HDR-1X1/2.54 1
18 10 R32,R33 0805 2
19 1n/NP0 C27A 0805 1
20 220p C3 0805 1
21 100p C2A 0805 1
22 100n C13,C0 0805 2
23 1u C2 0805 1
24 Energy-Processor JP1B HDR-F-2.54_1X5 1
25 47k R9 0805 1
26 220 R4 0805 1
27 470k R2 0805 1
28 10M R1 0805 1
29 100k R13 0805 1
30 MMBD770T1G D1 SOT-323-3_L2.0-W1.3-P1.30-LS2.1-BR 1
31 1n C27B WIMA 5MM 3.5X7.2 1
32 Energy-Processor JP1A HDR-F-2.54_1X3 1
33 100p WIMA C2B WIMA MKS2 5MM 1
34 TLV3544IDR U1 SOIC14 1


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