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Std edition STM8S001J3M3

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License: CC-BY-SA 3.0

Project source: Cloned from STM8S001J3M3_JX

Published Time: 2021-12-13 17:30:27
  • 1.6w
  • 0
  • 2
Description

High-performance STM8 core, three-stage instruction pipeline, main frequency up to 16M 8k FLASH, 1k RAM, 128Byte true EEPROM 3 master clock sources to choose from: HSE, HSI, LSI low power mode: wait, active-halt, halt The peripheral clock can be turned off independently, power-up and power-down reset embedded 32 midrange vectors, up to 5 external interrupts 2 16-bit timers, an 8-bit basic timer SPI single-line interface (up to 8Mbit/s), IIC (up to 400kbit/s) UART (SmartCard, lrDa, LIN's main mode) 3-way 10-bit ADC, individual/continuous/buffered operating mode 5-way universal IO port, inline single-line download and simulation interface SWIM

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design drawing
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ID Name Designator Footprint Quantity
1 1μF/20V C1 CA_3216_JX 1
2 100nF/50V C2,C5 0603_C_JX 2
3 1μF/50V C3,C4 0603_C_JX 2
4 SW_PUSH_JX KEY SW_PUSH_6MM_H5MM_JX 1
5 Blue/LED LED1 0603_D_JX 1
6 Green/LED LED2 0603_D_JX 1
7 Red/LED LED-PWR 0603_D_JX 1
8 0.96OLED_4P_Module_JX P1 0.96OLED_4P_MODULE_JX 1
9 M_2.54_1*4P_JX P2 M_2.54_1*4P_JX 1
10 XH_2501R_2P_Locked_JX P3 XH_2501R_2P_LOCKED_JX 1
11 M_2.54_2*3P_JX P4 M_2.54_2*3P_JX 1
12 M_2.54_1*8P_JX P5 M_2.54_1*8P_JX 1
13 M_R_2.54_1*3P_JX P6 M_2.54_1*3P_JX 1
14 M_B_2.54_1*3P_JX P7 M_2.54_1*3P_JX 1
15 4.7k/1% R1 0603_R_JX 1
16 10k/1% R2,R3 0603_R_JX 2
17 SW_SK-12D02_JX SW1 SW_SK-12D02_JX 1
18 STM8S001J3M3_JX U1 SOP8_150MIL_JX 1
19 SC662K-3.3_JX U2 SOT23_JX 1
20 LOGO_EASYEDA-BOTTOM U5 LOGO_EASYEDA-BOTTOM 1

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