Altera MAX EPM7xxx programming board

Ongoing

STD Altera MAX EPM7xxx programming board

FPGA

Digital

License: Public Domain

Mode:

Editors' pick

Update time： 2022-05-01 12:58:27

Creation time： 2020-01-06 11:29:57

Description

A simple JTAG programming/development board for the Altera/Intel MAX (v1) EPM7xxx series. It provides the ability to add an onboard clock or connect to an external clock.

* It was found that R1 should not be connected but pins should be soldered into the holes of R1 but not linked between holes for the chip to be detected properly in Quartus II via the Altera blaster driver.

* C1 and R5 are optional.

* A jumper should be added to J1 if the onboard clock is to be used.

* Add a jumper for J2 if the internal voltage and IO voltages are to be the same.

* The board can be powered via the relevant pins on H9 or H10.

* Please note that the EPM7128S chips tend to get quite hot at 5V over time and this appears to be normal from discussions with other people and my own chips.

Design Drawing

schematic diagram

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Sheet_2
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PCB

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large breadboard layout
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Small board
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BOM

BOM download Purchase Parts

ID	Name	Designator	Footprint	Quantity
1	100pF	C1,C3,C4,C5,C6	RAD-0.1	5
2	1uF	C2	CAP-D3.0XF1.5	1
3	PIN HEADER MALE 2X8	H1,H2,H3,H4,H5,H6,H7,H8,H9	PIN HEADER MALE 2X8	9
4	Header 2x6 2.54 Male	H10	HEADER 2X6 2.54 MALE	1
5	ALTERA USB BLASTER JTAG-10-2X5-SHROUDED	H11	2X5-SHROUDED	1
6	PIN HEADER 1X2	J1,J2	PIN HEADER 1X2	2
7	LED-3MM	LED1	LED-3MM/2.54	1
8	XTAL1	NO1	XTAL-DIP-14	1
9	10K	R1,R2,R3,R4	AXIAL-0.4	4
10	68R	R5	AXIAL-0.4	1
11	330R	R6	AXIAL-0.4	1
12	22R	R7	AXIAL-0.4	1
13	EPM7128SLC84	U1	PLCC84_PTH-SKT	1
14	EPM7032SLC44-10N	U2	PLCC44PA	1