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Update time：
2021-03-15 21:20:23
Creation time：
2020-04-19 18:55:06
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Design Drawing
Design Drawing
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vlc_phy_fec
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vlc_phy_fec_encoder_2nd_level
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vlc_phy_fec_rs_encoder_3rd_level
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vlc_phy_fec_interleaver_3rd_level
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vlc_phy_fec_deinterleaver_3rd_level
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vlc_phy_rs_decoder_3rd_level
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vlc_phy_convolutional_encoder_3rd_level
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vlc_phy_viterbi_wrapper
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vlc_phy_fec_decoder_2nd_level
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vlc_phy_fec_rs_encoder_3rd_level copy
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vlc_phy_fec_controller
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4x1_buffer
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vlc_phy_puncturing
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convolutional_encoder
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vlc_phy_depuncturing
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vlc_phy_fec_encoder_2nd_level_new
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vlc_phy_viterbi_decoder_3rd_level copy
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vlc_phy_fec_decoder_2nd_level_new
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vlc_phy_depuncturing_new
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vlc_phy_puncturing_new
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generic_interface_protocol
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vlc_phy_convolutional_encoder_3rd_level_new
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flop_cascade
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| ID | Name | Designator | Quantity |
|---|---|---|---|
| 1 | DFF_EN_RST | U4,U5,U6,U9,U12,U13 | 6 |
| 2 | xor_gate | U14,U15,U17,U20,U21,U18,U19,U22 | 8 |
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