GEN-P001-0-FPGA Module Cyclone 10 LP

This is a FPGA module PCA based around the Cyclone 10 LP, breaking out to two Terasic / Altera standard 40-pin headers. It supports the Cyclone 10 LP devices 10CL016, 10CL040 and 10CL055 (using vertical migration). The board also supports USB 2.0 and Gigabit Ethernet Interfaces. The USB interface also doubles as a entry point for flash access without requiring an official JTAG programmer. This board is relatively low power (at least where Altera FPGAs are concerned), and can run from USB power. The board also supports the low voltage variants of the Cyclone 10 LP devices through a simple change to the core regulator. Note that if using 1.0V as a core voltage, the Ethernet PHY will no longer be an option. This board has finished all initial testing with a 40K Cyclone 10 LP placed. Both the USB and Ethernet PHYs have been verified to work correctly. All voltage rails and clocks are spot on as well. Configuration via JTAG, and Active Serial boot from flash are also functioning. This design is a success with only a single known issue! In the future I'll be uploading a refernce project and publishing a full reference manual. Known Issues: 1. There is a jumper to select whether the board is powered by USB or from the external J1/J2 connectors. If this jumper is open and no power is supplied from the J1/J2 and USB is connected, it seems the board attempts to power through the USB PHY via the VCC_IO connection. This will damage the USB PHY if left in this state over time. This issue has been fixed in V1.1 of the PCB by connecting the USB PHY VCC_IO to the USB +3V3 rail rather than the board +3V3.