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2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
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2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
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STD DVI Output Test
License: Public Domain
Mode: Editors' pick
- 1
Update time：
2022-10-25 15:17:17
Creation time：
2020-11-13 09:05:22
Description
A simple PCB (initially designed to test the design for a DVI video output from a Cyclone EP4CE6 FPGA) for the EasyFPGA dev board at 480p, 720p and even successfully tested at 1080p.
Design Drawing
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | 100n | C1,C2 | C0402 | 2 |
| 2 | C0603 | C3,C4,C5,C6,C7,C8,C9,C10 | C0603 | 8 |
| 3 | 1nF | C11 | C1206 | 1 |
| 4 | 100n | C12 | C0805 | 1 |
| 5 | 100n | C13,C14 | C0603 | 2 |
| 6 | 10uF/16V | C60,C63 | CASE-A_3216 | 2 |
| 7 | 100nF | C61,C62 | C0805 | 2 |
| 8 | BAT46WH,115 | D1 | SOD-123F_L2.8-W1.8-LS3.7-RD | 1 |
| 9 | MF-PSMF010/24X | F1 | F0805 | 1 |
| 10 | X6521WV-2×22H-C30D60 | H1 | HDR-TH_44P-2.54-V-M-R2-C22-S2.54 | 1 |
| 11 | PTN3366BSMP | IC1 | QFN32-EXT | 1 |
| 12 | 10K | R1,R2,R4,R5,R6,R7,R9 | R0402 | 7 |
| 13 | 12.4K 1% | R3 | R0402 | 1 |
| 14 | 50R | R8,R10,R11,R12,R13,R14,R15,R16 | R0603 | 8 |
| 15 | 100R | R17,R19,R21,R23 | R0603 | 4 |
| 16 | 1M | R18 | R1206 | 1 |
| 17 | 10R | R43 | 1206 | 1 |
| 18 | DSIC02LS-P_C516637 | SW1 | SW-SMD_DSIC02LS-P | 1 |
| 19 | 10029449-111RLF | U1 | HDMI | 1 |
| 20 | AMS1117-3.3 | U13 | SOT-223-4_L6.5-W3.5-P2.30-LS7.0-BR | 1 |
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