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STD 2-input CMOS NAND Gate
2-input CMOS NAND Gate
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Update time：
2018-11-28 20:44:03
Creation time：
2018-10-14 08:36:51
Description
Description
2-input CMOS NAND gate
Design Drawing
Design Drawing
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| ID | Name | Designator | Quantity | Mounted |
|---|---|---|---|---|
| 1 | PMOS_D4 | M1,M4 | 2 | Yes |
| 2 | NMOS_D4 | M2,M3 | 2 | Yes |
| 3 | PULSE(5 0 0n 1n 1n 10u 20u) | V1 | 1 | No |
| 4 | PULSE(5 0 0n 1n 1n 5u 10u) | V2 | 1 | No |
| 5 | 5 | V3 | 1 | No |
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