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STD CPU project - Clock module
CPU project - Clock module
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Update time：
2018-05-13 12:44:10
Creation time：
2018-05-13 10:02:56
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | LM555CMM | U1,U5,U9 | TSSOP8_3 | 3 |
| 2 | 1uF | C1,C2 | CAP-CBB-6.5*4.0 | 2 |
| 3 | 100K | U2 | RESISTOR | 1 |
| 4 | 1K | U3,U7 | RESISTOR | 2 |
| 5 | 1M | U6 | RESISTOR | 1 |
| 6 | Switch3x4x2 | KEY1 | KEY-3.0*4.0 | 1 |
| 7 | SWITCH-SPDT | S1 | SWITCH-SPDT | 1 |
| 8 | AND2EE | U4,U11,U13 | NONE | 3 |
| 9 | OR | U8 | NONE | 1 |
| 10 | Inverter | U10,U12 | NONE | 2 |
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