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Update time：
2021-04-07 14:49:59
Creation time：
2015-10-27 15:12:16
Description
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Design Drawing
Design Drawing
schematic diagram
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Memory
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Display + Driver
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Full Adder
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Full Adder
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Dual Full Adder/Subtractor
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Counter
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Input
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Full Circuit Mockup
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Block Diagram
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Memory2
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Memory
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Full Circuit2
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Counter Sequence Test
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Counter Reset Test
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Counter Sequence Test
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Input Test Circuit
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Dual Full Adder With Gates
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D-Type Latch Test Plan
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Not Gate Test Plan
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NAND Gate Test Plan
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XOR Gate Test Plan
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Complete Circuit Diagram
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Memory Test Plan
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Memory Test Plan CM
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Dual Full Adder With Gates Test
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Display + Driver Test
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Block Diagram
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Demultiplexer Gate Test Plan
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PCB
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| ID | Name | Designator | Quantity |
|---|---|---|---|
| 1 | INVEE | U1,U6,U8,U9,U5,U16,U17,U7,U10,U11,U12,U4,U21,U22,U25,U13 | 16 |
| 2 | none | NONE | 1 |
| 3 | S4301B | LED1,LED2 | 2 |
| 4 | 1.2k | R1,R2,R7,R8,R9,R10,R11 | 7 |
| 5 | BCD to Seven Segment Decoder | U1,U24 | 2 |
| 6 | NAND2EE | U2,U3,U4,U8,U9,U13,U14,U15,U16,U17,U18,U19,U20,U26,U27,U28,U29,U30,U5 | 19 |
| 7 | XOR2 | U1,U2,U6,U7,U11,U12,U14,U15 | 8 |
| 8 | AND2EE | U3,U4,U8,U9 | 4 |
| 9 | OR2EE | U5,U10,U13,U16 | 4 |
| 10 | FULLADDEE | U1,U2,U12,U13 | 4 |
| 11 | 2.2k | R1,R2,R3,R4,R5,R6 | 6 |
| 12 | SPST_OFF | F,CANCEL,SWL,SWH,S1,S2,BIT1,BIT2,BIT3,NG | 10 |
| 13 | NMOS_D | M1,M2 | 2 |
| 14 | 10k | R1,R2,R3,R4,R5 | 5 |
| 15 | DFFEE | U5,U6,U7,U8,U9,U10,U11 | 7 |
| 16 | MUX21EE | U14,U15 | 2 |
| 17 | DEMUX12EE | U18 | 1 |
| 18 | 4511 | U19 | 1 |
| 19 | Logic Analyser | U1 | 1 |
| 20 | Function generator | U2,U1 | 2 |
| 21 | 4 Input Picoscope | U7,U3 | 2 |
| 22 | D-Type Latch | NONE | 1 |
| 23 | 6 Input Logic Analyser | U11 | 1 |
| 24 | 7 Input Logic Analyser | U11 | 1 |
| 25 | 9 Input Logic Analyser | U14 | 1 |
| 26 | 12 Input Logic Analyser | U3 | 1 |
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