© 2024 EasyEDA Some rights reserved ISO/IEC
1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
4.For enterprises, more professional users
STD Z80 Computer
Mode:
ID | Name | Designator | Footprint | Quantity |
---|---|---|---|---|
1 | 0.1UF | C1,C2,C3,C4 | CAP-CBB-10.0*4.5 | 4 |
2 | 1uF | C5 | CAP-TH_BD4.0-P1.50-D0.8-FD | 1 |
3 | 220uF | C6 | CAP-TH_BD4.0-P1.50-D0.8-FD | 1 |
4 | 0.1uF | C7 | CAP-TH_BD4.0-P1.50-D0.8-FD | 1 |
5 | Board Clock Enable | JP1 | JUMPER2 | 1 |
6 | Board Reset Enable | JP2 | JUMPER2 | 1 |
7 | RESET SW1 | KEY1 | KEY-TH_4P-L12.0-W12.0-P5.00-LS13.4 | 1 |
8 | φ3 Red | LED1 | LED-TH_2PIN-L3.50-W3.80-PITCH2.28-L | 1 |
9 | XTAL | NO | XTAL-DIP-14 | 1 |
10 | CPU Bus A0-A7 | P1 | PINHD-1X8 | 1 |
11 | CPU Bus A8-A15 | P2 | PINHD-1X8 | 1 |
12 | Data Bus A0-A7 | P3 | PINHD-1X8 | 1 |
13 | Z80 CPU Header | P4 | Z80 CPU HEADER | 1 |
14 | 10K | R1,R2,R3 | RES-TH_BD1.9-L3.3-P7.30-D0.5 | 3 |
15 | 220k | R4 | RES-TH_BD1.9-L3.3-P7.30-D0.5 | 1 |
16 | 330 | R5 | RES-TH_BD1.9-L3.3-P7.30-D0.5 | 1 |
17 | Z84C0020P Z80 CPU | U1 | DIP-40 | 1 |
18 | 64k x 8 bit SRAM | U2 | SKINNY-32 | 1 |
19 | W27C512 | U3 | DIP-28-600 SOCKET | 1 |
20 | SN7404N | U4 | DIP14 | 1 |
21 | 7805 | U5 | TO-220-3_L10.0-W4.5-P2.54-L | 1 |
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